Memory integrated circuit device having self reset circuit...

Details Memory integrated circuit device having self reset circuit... Memory integrated circuit device having self reset circuit...

2005-06-21

2005-06-21

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S198000

Reexamination Certificate

active

06909653

ABSTRACT:
The invention provides a semiconductor integrated circuit device having a signal transmission path realizing high speed and low power consumption with a simple configuration. The device has a signal transmission path for transmitting a signal by discharging one of first signal lines corresponding to complementary input signals in a plurality of first signal lines precharged by a precharge circuit, and a self reset circuit for detecting the discharge level of the pair of signal lines corresponding to the complementary signals out of the plurality of first signal lines and operating the precharge circuit at a timing later than the period of discharging.

REFERENCES:
patent: 6504774 (2003-01-01), Yoon et al.
patent: 6778447 (2004-08-01), Hsu et al.
patent: 61-144788 (1984-12-01), None
patent: 5-047180 (1991-08-01), None
Geordie Braceras, Alan Roberts, John Connor, Reid Wistort, Terry Frederick, Marcel Robillard, Stu Hall, Steve Burns and Matt Graf, “A 940 MHz Data-Rate 8Mb CMOS SRAM”, 1999 IEEE International Solid-State Circuits Conference, 2 pages.

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