Memory incorporating column register and method of writing...

Details Memory incorporating column register and method of writing... Memory incorporating column register and method of writing...

2001-09-13

2002-05-07

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S185230, C365S218000

Reexamination Certificate

active

06385096

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 99-12149, filed Sep. 29, 1999, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory devices, and more particularly to a column register suitable for an integrated circuit memory for instance in EEPROM technology, of the serial or parallel type, and a method of writing in said memory.
2. Description of the Prior Art
Such a memory contains cells arranged in a matrix of rows and columns. A memory cell memorizes the value of one bit in the memory. The cells of a same column are connected to a same connection line, classically depicted vertically and called bit line. Also, cells of a same row are connected to a same connection line, classically depicted horizontally and called word line.
As shown in
FIG. 1
, a cell M comprises a floating gate transistor TGF forming a non-volatile memorization element whose drain is connected to the bit line BL via a selection transistor TS, which is an N-type MOS transistor. In operation, the sources of the floating gate transistors of a same line are connected to ground, in general via another selection transistor (not shown) common to several adjacent cells. The gate of the floating gate transistor TGF is connected to a command gate line CG. That of the selection transistor TS is connected to the word line WL.
The erasure and programming of an EEPROM cell are obtained by the tunnel (“Fowler Nordheim”) effect. To this end, a high programming voltage VPP on the order of 18 volts is generated by any adapted means from the memory's supply voltage VCC, which is on the order of 5 volts.
An erased cell is a cell in which the floating gate of transistor TGF is negatively charged. In order to erase a cell, it is then necessary to supply it with voltages enabling to “trap” free electrons of the floating gate. Accordingly, it is necessary to apply the voltage VPP on line CG and on line WL, and to apply a zero voltage on line BL or to set that line to a high impedance state. The erased state of a cell corresponds for example to the memorization of a binary data 1.
A programmed cell is a cell in which the floating gate of transistor TGF is positively charged. To program a cell, it is therefore necessary to supply it with voltages capable of “snatching” electrons from the floating gate. Accordingly, it is necessary to apply the voltage VPP on line BL and on line WL, and to apply a zero voltage to line CG. The programmed state of a cell corresponds e.g. to the memorization of a binary data 0.
According to the above example, the writing of any binary value in a cell comprises a step of erasing the cell (so that it memorizes the binary data 1), then, when the binary data to be written is 0, a step of programming the cell. The initial erasure step at the programming step serves to control the charge of the floating gate under all circumstances. The programming step is conditional in the sense that it only takes place if the binary data to be written is 0.
In order to implement the programming step, the memory comprises, for each bit line, a high-voltage memorization and switching latch, or more simply a high-voltage latch. This latch forms part of a register known as a bit line register or a column register. Such a latch has a twofold function. Firstly it serves to memorize a binary data for the purpose of writing in a cell. Secondly, it serves to bring the bit line to which the cell is connected to voltage VPP, if the binary data to be written is 0. This second function of the latch is referred to as conditional switching.
FIG. 2
shows the diagram of a high voltage latch as known in the state of the art.
The latch BHT shown in
FIG. 2
first of all comprises high voltage memorization means for provisionally memorizing a binary data 1 or 0, respectively in the form of a high voltage VPP or a zero voltage.
These means classically comprise two inverters I
1
and I
2
connected “head-to-tail” between a node A and a node B so as to produce a memorization effect. They are high voltage inverters in the sense that they can receive and deliver a voltage of either zero or VPP. They are classically CMOS technology inverters, i.e. they comprise a P-type MOS transistor and an N-type MOS transistor in series between the high voltage source VPP and ground, the gates of the two transistors being connected together and the output of the inverter being taken at the node corresponding to the common source of the two transistors. By convention, the output of the memorization means is taken at node B and their input is taken at node A. In other words, the binary data stored by the latch is 0 when node B is brought to the zero potential (ground potential) and is 1 when node B is brought to the high voltage VPP (potential referenced with respect to ground).
The high voltage latch BHT also comprises loading means, for loading a binary data in the high voltage memorization means.
These loading means firstly comprise an N-type transistor designated N
1
connected to node A by its drain and to a node R by its source. In operation, the node R is connected to ground via a selection transistor (not shown). The gate of transistor N
1
receives a signal DATA bar which is a low voltage signal (i.e. whose level is either zero or equal to VCC) representing the inverse of the binary data to be written. In other words, the level of signal DATA bar is zero if the binary data to be written is 1 and is equal to VCC if the binary data to be written is 0. When its level is equal to VCC, the signal DATA bar serves to bring node B to the VPP voltage, which loads the binary value 1 into the high voltage memorization means I
1
, I
2
.
Secondly, the loading means comprise another N-type MOS transistor, designated N
2
, having its drain connected to node B and its source to node S. In operation, the node R is connected to ground either directly or via another selection transistor (not shown). The gate of transistor N
2
is connected to a node T to receive a reset to zero signal RLAT, which is also a low voltage signal. When its level is at VCC, this signal serves to bring node B to ground potential, so loading the binary value 0 into the memorization means I
1
, I
2
.
The loading of a binary data in the memorization means I
1
, I
2
is carried out in two stages: at a first stage, the signal RLAT passes to VCC, so connecting node B to ground via the transistor N
2
which is conducting, so that a 0 is loaded into the memorization means I
1
, I
2
; The signal RLAT then returns to zero to block transistor N
2
; at a second stage, the inverse of the binary data to write is brought to the gate of transistor N
1
by means of the signal DATA bar, so that node A is brought to ground potential via transistor N
1
only when the binary data to be written is 0, which then has the effect of loading the binary value 1 into the memorization means I
1
, I
2
.
The high voltage latch BHT further comprises conditional switching means to bring or not bring to the voltage VPP the bit line BL to which the cell is connected depending on the value memorized by the high voltage memorization means.
These conditional switching means comprise an N-type MOS transistor designated SW connected by its gate to the output of the high voltage memorization means I
1
, I
2
(i.e. at node B), to the bit line BL by its source and by its drain to the high voltage supply source VPP via an N-type MOS transistor designated WRT. The gate of transistor WRT receives a control signal WRMD which makes it conducting during the memory write operations (i.e. in the write mode) and which blocks it during the memory readout operations (i.e. in the read mode). Transistor WRT thus has the function of isolating the bit line BL from the high voltage VPP in the read mode. In the write mode, transistor SW provides the function of conditionally switching the high voltage latch since it allows to bring the bit line B

Affiliated with

Also associated with

Rating

Memory incorporating column register and method of writing... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory incorporating column register and method of writing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory incorporating column register and method of writing... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2823718