Memory I/O driving circuit with reduced noise and driving...

Details Memory I/O driving circuit with reduced noise and driving... Memory I/O driving circuit with reduced noise and driving...

2006-04-11

2006-04-11

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S191000, C326S083000, C326S086000, C327S108000, C327S112000

Reexamination Certificate

active

07027332

ABSTRACT:
A memory driving circuit has a register for receiving a new-coming data and a delayed clock, and exporting a current-existing data. The delayed clock has a delay to a clock. A pre-detecting circuit receives the current-existing data, the new-coming data, and a pre-enable signal, and exports an output signal. Wherein, the current-existing data is compared with the new-coming data. The output signal indicates a disable state if the two data are the same. Otherwise, the output signal indicates an enable state, wherein the pre-enable signal is also used to enable or disable the pre-detecting circuit. An output driving circuit receives the current-existing data and an enabling signal, and exports a first output signal. A pre-driving circuit receives the output signal of the pre-detecting circuit and an enable control signal, and exports a second output signal. An I/O pad receives the first output signal and the second output signal.

REFERENCES:
patent: 4779013 (1988-10-01), Tanaka
patent: 5497113 (1996-03-01), Uber
patent: 5539341 (1996-07-01), Kuo
patent: 5670894 (1997-09-01), Takaishi et al.
patent: 6411120 (2002-06-01), Hung et al.

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