Memory having test circuit

Details Memory having test circuit Memory having test circuit

2007-08-28

2007-08-28

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S723000

Reexamination Certificate

active

11013870

ABSTRACT:
A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first set of pass/fail signals for the memory cells into a second pass/fail signal, latch the second pass/fail signal in response to a data valid signal, maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test, combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal, and pass the fourth pass/fail signal to a third test circuit.

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