Memory having output buffer enable by level comparison and metho

Details Memory having output buffer enable by level comparison and metho Memory having output buffer enable by level comparison and metho

1992-07-27

1993-11-02

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518902, 365233, 365177, G11C 700

Patent

active

052589510

ABSTRACT:
A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

REFERENCES:
patent: 3760194 (1973-09-01), Lutz et al.
patent: 4467455 (1984-08-01), Sood
patent: 4763303 (1988-08-01), Flannagan

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