Memory having bit line load with automatic bit line precharge an

Details Memory having bit line load with automatic bit line precharge an Memory having bit line load with automatic bit line precharge an

1994-03-08

1995-05-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

36518908, 36518911, 365177, 3652256, 365204, G11C 700

Patent

active

054167442

ABSTRACT:
A bit line load (380) is coupled to a bit line pair and includes bipolar pull up transistors (389, 403), P-channel load transistors (390, 404), a NAND logic gate (395), and a P-channel equalization transistor. The NAND logic gate (395) senses a differential voltage on the bit line pair, and provides an equalization signal. When a write control signal indicates the end of a write cycle, the equalization signal initiates precharge and equalization of the bit line pair.

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Terry I. Chappell et al., "A 2ns Cycle, 4ns Access 512kb CMOS ECL SRAM", Feb., 1991 IEEE International Solid-State Circuits Conference, pp. 50, 51 & 288.

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