Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-08-09
2011-08-09
Abraham, Esaw T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S758000, C714S799000
Reexamination Certificate
active
07996734
ABSTRACT:
An error correction code system for a memory is provided. The memory is provided with a parity array that is directly accessible. An embodiment of the error correction code system includes writing and reading test data directly to the parity array. The data read from the parity array is compared with the test data written to the parity array to detect errors.
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Earle Adrian
Joshi Vineet
Rao Raviprakrash S.
Abraham Esaw T
Slater & Matsil L.L.P.
Taiwan Semiconductor Manufacturing Company , Ltd.
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