Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-03-16
2002-05-28
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S230030
Reexamination Certificate
active
06396760
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit memory devices, and more specifically to an embedded memory having a column redundancy scheme.
BACKGROUND OF THE INVENTION
Random defects occurring during the manufacturing process of an integrated circuit memory device can render non-redundant elements of an integrated circuit memory device, such as a memory column, defective. For example, particle contamination during the manufacturing process may cause broken or shorted out columns, bit defects, and/or locked columns.
Redundant elements of an integrated circuit memory device, such as redundant columns, are used to compensate for these random defects. Initial testing of an integrated circuit memory occurs after the manufacturing process. During initial testing of an integrated circuit memory device, defective elements are replaced by non-defective elements referred to as redundant elements. Thus, redundant columns may be used in a scheme to replace defective prime columns, discovered during initial testing of the integrated circuit memory device. The use of redundant elements is important in increasing the overall yield of an integrated circuit memory device.
With ever increasing densities and smaller feature sizes in integrated circuit memory devices, cell redundancy has become more and more important to the proper functioning of larger memory devices. Most memories now require column redundancy in which a portion of the memory cell array is designated as a redundant memory section. When a defective portion of the main memory exist, then the memory cells of the redundant memory section are accessed. On-chip logic circuitry is employed to store defective main memory addresses and to facilitate writing and reading of data to the redundant memory. This logic circuitry includes multiple fuse groups wherein individual fuses within a fuse group are either open or closed to represent a logic state. Each fuse group forms a logic word corresponding to an address of a defective cell or group of cells in the main memory. To enable use of the redundant column a set of fuses are, generally, cut or blown.
FIG. 1
a
illustrates a previous technique to shift an input-output circuit (IO) to an operational memory column from a faulty memory column. In this previous technique, if a fault exists in an 8, 16, or 32 column-multiplexing memory scheme, then in order to shift an IO to an operational memory column, the fuse corresponding to the faulty memory column is blown and every fuse downstream of that faulty memory column is blown. For example, memory column
3
is illustrated as being a faulty component. Fuse
3
is the fuse associated with memory column
3
. Fuse
3
is blown as indicated by storing a logical
1
. Additionally, each fuse downstream of the faulty memory column, Fuse
4
through Fuse
7
is also blown. Due to Fuse
3
through Fuse
7
being blown, IO
3
through IO
7
shift reading and writing operations to an adjacent memory column. However that technique typically causes several problems. One problem is that additional power is required to blow all those fuses. Further, the reliability of blowing fuses decreases as the number of fuses that need to be blown increases. As the number of fuses that need to be blown increases, the statistical probability increases that one of those fuses that is supposed to be blown will in fact not be blown.
SUMMARY OF THE INVENTION
An apparatus and method in which a single fuse is asserted in a memory bank having a redundancy memory column structure. The assertion of the single fuse causes two or more of the input-output circuits to shift away from a primary memory column to a substitute memory column.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
REFERENCES:
patent: 5583463 (1996-12-01), Merritt
patent: 5608678 (1997-03-01), Lysinger
patent: 5859801 (1999-01-01), Poechmueller
patent: 6084819 (2000-07-01), Kablanian
patent: 6091620 (2000-07-01), Kablanian
patent: 6104663 (2000-08-01), Kablanian
Betty Prince, Semiconductor Memories, copyright 1983, pp. 150-303.
Behera Niranjan
Sampigethaya Shreekanth K.
Blakely , Sokoloff, Taylor & Zafman LLP
Fears Terrell W.
Virage Logic Corporation
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