Memory fault isolation apparatus and methods

Details Memory fault isolation apparatus and methods Memory fault isolation apparatus and methods

2000-11-27

2003-09-16

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000, C714S723000

Reexamination Certificate

active

06622269

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductors and, more particularly, to improved apparatus and methods for testing memory elements on integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) are typically assembled into packages by physically and electrically coupling them to a substrate. One or more IC packages can be physically and electrically coupled to a printed circuit board (PCB) to form an “electronic assembly”. An “electronic assembly” can be part of an “electronic system”. An “electronic system” is broadly defined herein as any product comprising an “electronic assembly”. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, MP3 (Motion Picture Experts Group, Audio Layer 3) players, etc.), and the like.
Integrated circuits (ICs) typically contain one or more functional logic blocks (FLBs), such as a microprocessor, microcontroller, graphics processor, bus interface circuit, input/output (I/O) circuit, memory circuit, and the like. It is well known to provide combinations of FLBs that include one or more memory circuits. Such combinations can be provided on one or more ICs. For example, such a combination could include a microprocessor and a memory circuit on a single IC or on separate ICs. One such combination known in the art is a microprocessor and a cache memory on a single IC. Other combinations of processors and memory circuits are also known.
In the field of electronic systems there is an incessant competitive pressure among manufacturers to drive the performance of their equipment up while driving down production costs. This is particularly true regarding the testing of ICs. ICs must generally be tested before they are incorporated into an electronic assembly in order to verify that each component of each FLB, including any memory circuit, on the IC functions properly. It is desirable to thoroughly test ICs while at the same time minimizing the cost, time, and complexity of testing.
In testing memory circuits, it is known to employ a type of testing referred to as programmable built-in self-test (PBIST), as described for example in U.S. Pat. No. 5,640,509, assigned to the assignee of the present invention. According to one embodiment of U.S. Pat. No. 5,640,509, a PBIST circuit is provided as part of an IC that also includes a memory circuit. The PBIST circuit comprises a set of programmable registers that determine a test sequence to be performed on the memory circuit.
When a PBIST circuit determines that a memory failure has occurred, it is desirable to capture and examine not only the set of command, address, and data values corresponding to the read operation that generated the first mismatch, but also the same information for several subsequent read operations that were in the memory and PBIST pipelines when the failure was first detected. In prior art PBIST circuits, the circuitry for capturing several sets of command, address, and data values consumes a relatively large portion of the IC containing the PBIST circuits.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for a PBIST circuit that occupies minimal silicon area, as well as for methods of operating such a PBIST circuit.


REFERENCES:
patent: 5185871 (1993-02-01), Frey et al.
patent: 5487156 (1996-01-01), Popescu et al.
patent: 5627983 (1997-05-01), Popescu et al.
patent: 5640509 (1997-06-01), Balmer et al.
patent: 5699536 (1997-12-01), Hopkins et al.
patent: 5883843 (1999-03-01), Hii et al.

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