Memory error detection reporting

Details Memory error detection reporting Memory error detection reporting

2007-07-03

2007-07-03

Baker, Stephen M. (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C711S144000

Reexamination Certificate

active

10950797

ABSTRACT:
A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.

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