Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-06-21
2001-08-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S233100
Reexamination Certificate
active
06275428
ABSTRACT:
This application claims benefit of priority under 35USC §119 to Japanese Patent Application No. H11-175783, filed on Jun. 22, 1999, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a memory-embedded semiconductor integrated circuit device wherein a memory and a logic part are consolidated on one chip, and a method for testing the same.
2. Description of Related Art
In recent years, there have been proposed various semiconductor integrated circuit devices wherein a large scale memory macro is consolidated with a logic part, such as application specific integrated circuits (ASICs) and micro processors. In a memory-embedded LSI of this type, the usual operation of a memory macro is controlled by a signal from a logic part. For example, if a read instruction is given from the logic part, the memory macro outputs data of a selected address to the logic part. Similarly, if a write instruction is inputted from the logic part, data inputted simultaneously with the instruction are written at the address of the selected memory macro. In the memory-embedded LSI of this type, there are two methods for testing a memory macro. One method is a method for testing a memory macro by controlling the operation of the memory macro via a logic part without the need of a dedicated test circuit. The other method is a method for testing a memory macro regardless of a logic part, by providing a dedicated test circuit and a testing input/output pad. Since the former increases a vector length in a large scale memory macro, the latter test method is generally used.
A first example of a conventional memory-embedded semiconductor integrated circuit device, which is provided with a dedicated test circuit, is shown in FIG.
26
. In this first conventional example, a memory-embedded semiconductor integrated circuit device
100
comprises a logic part
3
comprising a gate array or a standard cell, a memory macro
5
, and a test circuit
110
for evaluating the operating characteristics of the memory macro
5
. Furthermore, the memory-embedded semiconductor integrated circuit device
100
is provided with an I/O part
2
, which has a test input terminal group
20
of n terminals and a test output terminal group
21
of m terminals, on the periphery thereof.
The test circuit
110
has a test signal generator
140
. The test signal generator
140
is connected, via a test input wire
23
, to the test input terminal group
20
, to which an n-bit test command is inputted from a tester (not shown). The test circuit
110
is also connected to the test output terminal group
21
via a test output wire
24
to output m-bit test data. This test signal generator
140
decodes the test command to generate a test signal
17
a
for carrying out the test operation of the memory macro
5
.
In general, as shown in
FIG. 27
, the memory macro
5
has a plurality of memories
70
, each of which comprises a memory cell array
71
, a column address decoder
72
and a row address decoder
74
. When the test signal
17
a
is inputted to a memory cell array
71
, which is to be tested, in the memory macro
5
, an m-bit test data output
17
b
is outputted from the memory cell array
71
to the test circuit
110
. This test data output
17
b
is outputted to the test output terminal group
21
via the test circuit
110
and the test output wire
24
. Then, on the basis of the test data output which has been outputted to the test output terminal group
21
, a tester (not shown) determines a pass/fail.
Furthermore, the memory macro
5
has a terminal for receiving an input
18
a
in a usual operation and a terminal for outputting a data output
18
b,
as well as a terminal for receiving the test signal and a terminal for outputting the test data output
17
b.
Then, a second example of a conventional memory-embedded semiconductor integrated circuit device is shown in FIG.
28
. In this second conventional example of the memory-embedded semiconductor integrated circuit device, the test circuit
110
of the memory-embedded semiconductor integrated circuit device in the first conventional example shown in
FIG. 26
is replaced with a test circuit
110
A, and the I/O part (not shown) is provided with a test clock input terminal
22
.
The test circuit
110
A comprises a flip-flop circuit
12
for incorporating an n-bit test command in synchronism with a clock, and a test signal generator
140
for decoding the output of the flip-flop circuit
12
to generate a test signal for carrying out the test operation of a memory macro
5
. Furthermore, although only one flip-flop circuit
12
is shown in the figure, n flip-flop circuits are provided in practice.
A test command outputted from a tester
40
is inputted to the flip-flop
12
via a lead wire
42
, a probe card needle
43
, a test input terminal group
20
and a test input wire
23
. A test clock outputted from the tester
40
is inputted to the flip-flop circuit
12
via a lead wire
42
, the probe card needle
43
, a test clock input terminal
22
and a test clock wire
25
, and inputted to the memory macro
5
as a clock input
17
c.
Furthermore, the m-bit test data output
17
b
outputted from the memory macro is outputted to a test output terminal group
21
via the test circuit
110
A and a test output wire
24
.
The wafer test for the second conventional example of the memory-embedded semiconductor integrated circuit device is carried out as follows. First, the probe card needle
43
is connected to the test input terminal group
20
, the test output terminal group
21
and the test clock input terminal
22
. Thereafter, from the tester
40
, a test command is inputted to the test input terminal group
20
, and a test clock is inputted to the test clock input terminal
22
.
Then, the test command inputted to the test input terminal group
20
is incorporated into the flip-flop circuit
12
in synchronism with the test clock which has been inputted to the test clock input terminal
22
, and then, outputted from the flip-flop circuit
12
in synchronism with the test clock to be an incorporated test command. This incorporated test command is decoded in the test signal generator
140
to be a test signal
18
a,
which serves to carry out the test operation of the memory macro
5
, to be fed to the memory macro
5
. Thereafter, an m-bit test data output
17
b
is outputted from the memory macro
5
to the test output terminal group
21
via the test circuit
110
A and the test output wire
24
. Then, the test data output
17
b
outputted to the test output terminal group
21
is fed to the tester
40
via the probe card needle
43
and the lead wire
42
. On the basis of this test data output
17
b,
the tester
40
determine a pass/fail.
Furthermore, in the second conventional example of the memory-embedded semiconductor integrated circuit device, the length and capacity of the test input wire
23
, the test output wire
24
and the test clock input wire
25
are different every product.
In the first conventional example of the memory-embedded semiconductor integrated circuit device with the above described construction, if a test is carried out when there are defects between the test input terminal group
20
and the input end of the memory macro
5
or when there are defects between the output end of the memory macro and the test output terminal group
21
, it is not possible to identify whether the defects exist in the memory macro
5
or the test path (e.g., the test input wire
23
and the test circuit
110
). Therefore, there is a problem in that it takes a lot of time to analyze the defects, so that it takes a lot of time to carry out the test.
In addition, in the first conventional example, there is some possibility that the wiring length between the test input terminal group
20
and the test circuit
110
is different from each other. Thus, there is a problem in that the wiring capacity of the test input wire
23
is different from each other to cause a skew be
Fukuda Ryo
Miyano Shinji
Wada Osamu
Dinh Son T.
Finnegan, Henderson, Farabow & Dunner, L.L.P.
Kabushiki Kaisha Toshiba
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