Memory devices having reduced interference between floating...

Details Memory devices having reduced interference between floating... Memory devices having reduced interference between floating...

2011-07-12

2011-07-12

Pham, Hoai v (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S201000, C438S211000, C257SE21209

Reexamination Certificate

active

07977190

ABSTRACT:
A floating gate memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another and methods of fabricating the same. Floating gate transistors are formed such that each of the floating gate transistors in the array has a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. Methods of fabricating such structures are also provided.

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