Memory devices

Details Memory devices Memory devices

1996-10-01

1998-02-03

Dinh, Son T.

Static information storage and retrieval

Systems using particular element

Negative resistance

365 49, 365240, G11C 700, G11C 1500

Patent

active

057152004

DESCRIPTION:

BRIEF SUMMARY
The present invention relates to methods and corresponding devices for handling and storing large amounts of data in a computer in an efficient manner which alloys repeated read and write operations to the memory.
The invention is particularly related to the storage and use of data in RAM, and has application for instance in computer graphics devices.
Computers include Random Access Memory (RAM) which is used during the operation of a computer to store data relevant to the operation of the computer, such as program information or graphics data. Such data is supported only while the computer is switched to provide power to the memory, but RAM is used due to its faster access speeds compared with permanent memory devices such as magnetic storage media.
For example, typical computer display systems have a display memory implemented in RAM which has stored in it information concerning the required parameters for each pixel of a screen display. This memory is repeatedly read and the information is passed to the display screen whereby the screen reflects the contents of the memory. When the computer wishes to alter the image displayed on the screen it acts to alter the corresponding information in the display memory, these changes subsequently being reflected on the actual screen. Therefore the performance of a graphics display system, and other sub-systems of the computer which utilizes RAM, is dependent to a large extent on the ability quickly to read and write data to and from the memory.
Many systems use Dynamic Memory (DRAM) to store the information because of the high density achieved by DRAM memory compared to Static Ram (SRAM), typically at least four times denser measured by silicon area per bit. This benefit is gained at the expense of speed of access to the memory, where SRAM of the required size will alloy memory cycles to occur at typically 30 ns intervals but DRAM will typically require 120 ns intervals. The rest of the system which is trying to modify the memory contents can work at SRAM speeds, so considerable effort is expended to design systems which use DRAM for cost benefits but achieve SRAM performance. The standard approach to this problem is to use cache memory techniques, applied at various levels of the system.
The lowest level at which this technique is applied is to use "page mode" DRAM cycles, where the memory device retains a row of bits read once from the two dimensional array of storage elements within the device, allows these bits to be read or modified at speeds nearly as fast as SRAM, them finally writes the modified row back into the DRAM storage array if needed. This can achieve about four times enhancement if many accesses are made to the same row without intervening accesses to other rows, but the advantage decreases as multiple real-time requests are made to the memory system, increasing the overhead of the initial read row and the final write row operations. The conventional solution to this second problem is to add First In First Out (FIFO) buffers onto each access path into the memory, allowing bursts of sequentially addressed values in the same row to be kept together. These FIFOs can take considerable area of silicon to implement.
The second level at which this technique is applied is to put a small SRAM within the memory, e.g. graphics controller, which is separate from the memory device, and use it to store information accessed from the DRAM in case it is needed again in the near future, in which case the requested data is provided from SRAM at SRAM speed. Multiple writes to the cache memory can also occur before the final result is written back into the DRAM.
The highest level of cache within the graphics controller is a simple "write buffer", which accepts the address and data from the host system and allows it to continue immediately. The write buffer contents are then written into the memory at slower speed. This technique speeds up operation as long as gaps occur between the write cycles, if they are continuous then the operations proceed at the slower rate of t

REFERENCES:
patent: 4685082 (1987-08-01), Cheung et al.
patent: 5383146 (1995-01-01), Threewitt
patent: 5450351 (1995-09-01), Heddes
patent: 5588130 (1996-12-01), Fujishima et al.

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