Memory device with surface-channel peripheral transistors

Details Memory device with surface-channel peripheral transistors Memory device with surface-channel peripheral transistors

2008-01-10

2009-12-29

Smith, Zandra (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S305000, C257S296000, C257SE21648, C257S021000, C257SE27089, C257SE27097

Reexamination Certificate

active

07638401

ABSTRACT:
A method of forming a memory device (e.g., a DRAM) including array and peripheral circuitry. A plurality of undoped polysilicon gates58are formed. These gates58are classed into three groups; namely, first conductivity type peripheral gates58p, second conductivity type peripheral gates58n, and array gates58a. The array gates58aand the first conductivity type peripheral gates58nare masked such that the second conductivity type peripheral gates58premain unmasked. A plurality of second conductivity type peripheral transistors can then be formed by doping each of the second conductivity type peripheral gates58p, while simultaneously doping a first and a second source/drain region84adjacent each of the second conductivity type peripheral gates58p. The second conductivity type peripheral gates58pare then masked such that the first conductivity type peripheral gates58nremain unmasked. A plurality of first conductivity type peripheral transistors are formed by doping each of the first conductivity type peripheral gates58n, while simultaneously doping a first and a second source/drain region82adjacent each of the first conductivity type peripheral gates58n.

REFERENCES:
patent: 2002/0027259 (2002-03-01), Ikemasu et al.

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