Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-07-26
2001-10-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S149000, C365S207000
Reexamination Certificate
active
06301175
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to dynamic memory integrated circuits and in particular the present invention relates to sensing circuits therein.
BACKGROUND OF THE INVENTION
Integrated circuit memories have become increasingly dense as the need for more memory storage increases. While fabrication techniques and design options have been fairly successful in maintaining steady increases in memory storage from design generation to generation, the need for new highly populated circuits continues.
A dynamic random access memory (DRAM) device is comprised of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit or digit lines, which are coupled to input/output lines through transistors used as switching devices. For each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available at on an I/O compliment line. Thus, each memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a word line in response to the row address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the column address. For a read operation the selected word line activates the access transistors for a given row address, and data is latched to the digit line pairs.
Conventional dynamic memories use memory cells fabricated as capacitors in an integrated circuit to store data. That is, a logical “1” is stored as a charge on the capacitor and the capacitor is discharged for a logical“0”. The pairs of digit lines are fabricated as metal lines on the integrated circuit and connected to the memory cells for transmitting data stored in the memory cells. Sense amplifiers are utilized to sense small differentials on the digit lines and drive the digit lines to full power supply rails for either reading the memory cells or writing thereto. Although unique fabrication techniques and processes have been developed to reduce the size of the memory cells and access circuitry, the physical spacing requirements for the digit line architecture creates a barrier to maximizing the available die area. That is, the reductions in memory cell size cannot be fully exploited due to the digit line pairs.
U.S. Pat. Nos. 5,625,588 and 5,684,749 describe a memory devices that includes a single ended sensing techniques. The equilibrate and pre-charge circuitry, however, may not be optimum for low voltage operation. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a sensing circuitry which reduces the need for die area while allowing low supply voltage operation.
SUMMARY OF THE INVENTION
The above mentioned problems with increasing the population of integrated circuit memories and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A dynamic memory circuit is described which uses sensing circuitry that reduces the number of metal digit lines needed to access the memory cells and reduces the need for boosted word line voltages.
In particular, one embodiment of the present invention provides an integrated circuit comprising a plurality of memory cell capacitors, and a plurality of access devices connected to the plurality of memory cell capacitors and a single digit line, each to selectively connect one of the plurality of memory cell capacitors to the single digit line. A differential sense amplifier circuit is provided that has first and second nodes each selectively connected to the single digit line through first and second isolation transistors. The first isolation transistor have a drain connected to the first node and a source connected to the digit single line. The second isolation transistor has a drain connected to the second node and a source connected to the single digit line. An equilibrate circuit is provided to equilibrate the first and second nodes to a pre-charge voltage level that is approximately a transistor threshold voltage above ground potential.
In another embodiment, a method of sensing data stored in a plurality of dynamic memory cell capacitors is provided. The method comprises equilibrating a sense amplifier circuit to a pre-charge voltage level that is approximately a transistor threshold voltage above ground potential. The sense amplifier circuit has a first node and a second node selectively connected to a single digit line through first and second isolation transistors. The first isolation transistor has a first terminal connected to the first node and a second terminal source connected to the single digit line. The second isolation transistor has a first terminal connected to the second node and a second terminal connected to the single digit line. The method includes providing an isolation signal to a gate of the second isolation transistor to electrically isolate the second node of the sense amplifier circuit from the single digit line, and sensing the data stored in a dynamic memory cell capacitor using a differential sense amplifier circuit.
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Seyyedy Mirmajid
Shirley Brian M.
Auduong Gene N.
Micro)n Technology, Inc.
Nelms David
Schwegman Lundberg Woessner & Kluth P.A.
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