Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-11-27
2003-05-13
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S230060, C365S194000
Reexamination Certificate
active
06563756
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
This application relies for priority upon Korean Patent Application No. 2000-75491, filed on Dec. 13, 2000, the entire contents of which are hereby incorporated herein by reference in their entirety as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a control of refreshing a DRAM.
2. Description of the Related Art
A general dynamic RAM (DRAM) requires a data refreshing process to preserve data stored in a cell.
Refresh is performed to restore the charge on a memory cell capacitor before leakage of charge reaches a predetermined level, because charge in the memory cell capacitor leaks along a semiconductor surface. Refresh is performed either by a certain instruction generated in a system (CAS before RAS refresh), or automatically under certain conditions (auto refresh). The refreshing process repeats the sensing of lost cell data and restores the lost cell data to its prior state through a sense amplifier. In general, refresh intervals are determined by the capacitance of a memory cell capacitor and size of a MOS transistor used in the memory cell.
As the integration density of memories increases, the number of refresh cycles increases with the number of memory rows to be refreshed. As a result, refresh time also increases. However, since in a system using a memory, required refresh time is reduced rather than increased, a method of relatively reducing refresh intervals has been used to make up for an increase in the number of refresh cycles increasing with the integration of memories.
One such method involves refreshing not one but several sub-memory cell array blocks at the same time for a refresh period. However, as the number of sub-memory cell array blocks refreshed at the same time increases, peak current and momentary power consumption increase, thereby increasing a peak level. Therefore, circuit design and power supply voltage metal routing in consideration of this point become difficult.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a memory device for reducing noise power levels generated in refreshing a plurality of sub-memory cell array blocks at the same time.
Accordingly, to achieve the above object, there is provided a memory device including a plurality of memory cell blocks, a block select unit, and a row decoder.
Each of the memory cell blocks includes a plurality of sub-memory cell array blocks, and the block select unit outputs a plurality of block select signals corresponding to a plurality of control signals generated by a block select address. The row decoder selects at least one memory cell block corresponding to at least one block select signal activated among the plurality of the block select signals and activates a word line of the selected memory cell block by responding to a row address. In a refresh mode, the block select unit selects N (a natural number) memory cell blocks among the plurality of the memory cell blocks and controls the row decoder to sequentially select N memory cell blocks after a predetermined delay.
The block select unit includes a non-delay type select circuit group for outputting a block select signal corresponding to a first control signal among the plurality of control signals, and an N−M (N minus M) delay type select circuit group for outputting a block select signal corresponding to a second control signal among the plurality of control signals and a signal activated in a refresh mode. Here, M is a natural number less than N.
The non-delay type select circuit group directly outputs a block select signal corresponding to the first control signal in a normal mode or a refresh mode, and the delay type select circuit group directly outputs a block select signal corresponding to the second control signal in a normal mode, and outputs a block select signal after a predetermined delay corresponding to the second control signal and a signal activated in the refresh mode.
The non-delay type select circuit group includes a plurality of non-delay type select circuits, and the delay type select circuit group includes N−M delay type select circuits each having different delay times.
The non-delay type select circuit includes a NAND gate, to one input of which a power supply voltage is applied, and to the other input of which one of the plurality of control signals is applied, and an inverter for inverting a signal output from the NAND gate. The delay type select circuit includes a delay unit for delaying the one control signal for a predetermined time, an inverter for inverting a signal activated in the refresh mode, a first NAND gate for responding to a signal activated in the refresh mode and an output signal of the delay unit, a second NAND gate for responding to the one of the plurality of control signals and an output signal of the inverter, and a third NAND gate for responding to output signals of the first and second NAND gates.
REFERENCES:
patent: 5644545 (1997-07-01), Fisch
Lam David
Samsung Electronics Co,. Ltd.
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