Memory device with reduced power dissipation

Details Memory device with reduced power dissipation Memory device with reduced power dissipation

1998-04-01

2000-05-09

Nelms, David

Static information storage and retrieval

Read/write circuit

Precharge

365210, G11C 700

Patent

active

06061286&

ABSTRACT:
A memory device comprises an array of memory cells arranged in rows and columns, a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows, a dummy column of dummy memory cells substantially identical to the memory cells, precharge means for precharging the columns and the dummy column at a precharge potential when no row is selected, and programming means for setting selected columns at respective programming potentials. The device comprises dummy memory cell preset means for presetting the dummy memory cells in a first logic state when no row is selected, dummy column programming means for setting the dummy column at a prescribed programming potential corresponding to a second logic state opposite to the first logic state, and first detector means for detecting that the dummy column has discharged from the precharge potential to the prescribed programming potential and for consequently enabling said plurality of gates. Each of the gates has an input coupled to a respective dummy memory cell so that the gate is disabled as soon as the respective dummy memory cell has switched from the first logic state to the second logic state.

REFERENCES:
patent: 5029135 (1991-07-01), Okubo
patent: 5751634 (1998-05-01), Itoh
European Search Report from European Patent Application No. 97830160.4, filed Apr. 3, 1997.

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