Memory device with reduced cell size

Details Memory device with reduced cell size Memory device with reduced cell size

2005-10-25

2005-10-25

Baumeister, B. William (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S260000, C438S261000, C438S593000, C438S588000, C438S264000, C257S213000, C257S314000, C257S315000, C257S319000, C257S410000

Reexamination Certificate

active

06958269

ABSTRACT:
A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.

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patent: 6754108 (2004-06-01), Forbes

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