Memory device with reduced cell area

Details Memory device with reduced cell area Memory device with reduced cell area

2008-07-08

2008-07-08

Ngo, Ngan (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C257SE21179, C257SE21422, C257SE21680

Reexamination Certificate

active

07396722

ABSTRACT:
The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.

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