Memory device with reduced buffer current during power-down...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189020, C365S201000, C365S229000, C365S230080, C365S233150

Reexamination Certificate

active

07933155

ABSTRACT:
A memory device comprises a memory array, at least one buffer coupled to the memory array, and test circuitry coupled to the buffer. The buffer comprises switching circuitry configured to multiplex first and second inputs of the buffer to a given output of the buffer based at least in part on a control signal generated by the test circuitry. The control signal is generated as a function of both a test signal indicative of a test mode of operation of the memory device and a power-down signal indicative of a power-down mode of operation of the memory device. The buffer further comprises current reduction circuitry responsive to the control signal for reducing an amount of current consumed by the buffer in the power-down mode of operation. The buffer may comprise an input data buffer or an address buffer of the memory device.

REFERENCES:
patent: 6058063 (2000-05-01), Jang
patent: 6794914 (2004-09-01), Sani et al.
patent: 2002/0191480 (2002-12-01), Matsumoto et al.
patent: 2006/0279308 (2006-12-01), Ong
patent: 2007/0147149 (2007-06-01), Yoon
patent: PCT/US2007/075811 (2008-06-01), None

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