Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-07-26
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S207000, C365S205000, C365S202000
Reexamination Certificate
active
06292417
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to dynamic memory integrated circuits and in particular the present invention relates to bit line circuitry therein.
BACKGROUND OF THE INVENTION
Integrated circuit memories have become increasingly dense as the need for more memory storage increases. While fabrication techniques and design options have been fairly successful in maintaining steady increases in memory storage from design generation to generation, the need for new highly populated circuits continues.
A dynamic random access memory (DRAM) device is comprised of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit or digit lines, which are coupled to input/output lines through transistors used as switching devices. For each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available at on an I/O compliment line. Thus, each memory cell has two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a word line in response to the row address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the column address. For a read operation the selected word line activates the access transistors for a given row address, and data is latched to the digit line pairs.
Conventional dynamic memories use memory cells fabricated as capacitors in an integrated circuit to store data. That is, a logical “1” is stored as a charge on the capacitor and the capacitor is discharged for a logical “0”. The pairs of digit lines are fabricated as metal lines on the integrated circuit and connected to the memory cells for transmitting data stored in the memory cells. The digit lines are typically pre-charged to an intermediate voltage level prior to reading a memory cell. Sense amplifiers are utilized to sense small differentials on the digit lines after a memory cell has been accessed and drive the digit lines to full power supply rails for either reading the memory cells or writing thereto.
Supply voltages for memory devices have been experiencing consistent reductions between memory device generations. This reduction in supply voltages creates problems with operating speeds. For example, sense amplifier speed can be reduced as the supply voltage reduces. Further, elevated word line and isolation device control signals are required at 1.8 volts supply levels.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device which can be operated at low supply voltages while maintaining comparable operating and data sensing speeds.
SUMMARY OF THE INVENTION
The above mentioned problems with memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification.
In particular, an illustrative embodiment of the present invention includes an integrated circuit memory comprising a plurality of memory cell capacitors, and a plurality of access devices connected to the plurality of memory cell capacitors and first and second digit lines. Each of the plurality of access devices selectively connects one of the plurality of memory cell capacitors to either the first or second the digit line. Sense amplifier circuitry is provided that has first and second sensing nodes each selectively connected to either the first or the second digit line. Control circuitry is coupled to the sense amplifier circuitry to provide a pre-charge voltage from the first and second sensing nodes to the first and second digit lines.
In another, a method is provided of operating a memory device comprising a pair of complimentary digit lines and sense amplifier circuitry. The method comprises equilibrating the pair of complimentary digit lines to a ground potential such that the pair of complimentary digit lines are discharged, pre-charging first and second sensing nodes of the sense amplifier circuitry to a pre-determined voltage level, and selectively coupling the first and second sensing nodes to the complimentary digit lines.
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Lam David
Micro)n Technology, Inc.
Nelms David
Schwegman Lundberg Woessner & Kluth P.A.
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