Memory device with precharge reinforcement circuit

Details Memory device with precharge reinforcement circuit Memory device with precharge reinforcement circuit

2001-12-31

2002-11-12

Nguyen, Viet Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S204000, C365S205000

Reexamination Certificate

active

06480434

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory device; and, more particularly, to a memory device capable of improving a characteristic of a bit line precharge time tRP.
DESCRIPTION OF THE PRIOR ART
In general, a dynamic random access memory (DRAM), one type of semiconductor memory device, selects a specific memory cell through a row decoder, and writes/reads data to/from the selected specific memory cell through bit lines. A bit line sense amplifier (BLSA) coupled to the bit lines amplifies the data.
FIG. 1
is a block diagram showing the structure of a conventional semiconductor memory device having a bit line sense amplifier. One cell array block shares two bit line sense amplifiers.
Referring to
FIG. 1
, a plurality of cell array blocks BLOCK
0
to BLOCKN are shared by one column decoder YDEC, and each cell array block is shared by two bit line sense amplifiers BLSA.
Here, the cell array blocks BLOCK
0
to BLOCKN are arrayed at positions corresponding to a word line (WL) and a bit line (BL), and are constituted by a cell array having a plurality of memory cells for storing the data. The bit line sense amplifier BLSA includes edge bit line sense amplifiers BLSA_EDGE and central bit line sense amplifiers BLSA. The edge bit line sense amplifiers BLSA_EDGE are disposed at the highest cell array block BLOCK
0
and the lowest cell array block BLOCKN, and the central bit line sense amplifiers BLSA are disposed between the cell array blocks.
In other words, while the central bit line sense amplifiers BLSA are disposed between the cell array blocks, the edge bit line sense amplifiers BLSA_EDGE are coupled only to the highest cell array block BLOCK
0
and the lowest cell array block BLOCKN in which there is no cell at one side thereof.
FIG. 2
is a circuit diagram showing the edge bit line sense amplifier BLSA_EDGE, a bit line control block containing peripheral circuits, and a cell array block according to the prior art. In the case where bit lines BL
0
and /BL
0
are precharged after the activation of word line WL
0
of the top cell array block BLOCK
0
, the operation of the bit line sense amplifier will be described with reference to FIG.
2
.
Referring to
FIG. 2
, the conventional edge bit line sense amplifier and control circuits include a cell array block
10
, a sense amplifier
20
, a precharge unit
30
, a block selection unit
40
and an equalization unit
50
.
The cell array block
10
is arrayed at a position corresponding to a word line WL
0
and a bit line pair BL
0
and /BL
0
, and is provided with a plurality of memory cell arrays for storing the cell data. The sense amplifier
20
senses and amplifies the cell data through the bit line pair BL
0
and /BL
0
coupled to the cell array block
10
.
The precharge unit
30
precharges the bit line pair BL and /BL
0
to a predetermined potential level in response to a bit line precharge control signal BLPG_
0
. The block selection unit
40
controls the connection between the block
10
and the sense amplifier
20
through the bit line pair BL
0
and /BL
0
in response to a bit line isolation signal BISL_
0
.
The equalization unit
50
is coupled between the block selection unit
40
and the cell array block
10
, and directly equalizes the bit line pair BL
0
and /BL
0
in response to a bit line equalization signal BLEQL_
0
.
Here, the precharge unit
30
includes a bit line precharge voltage applying terminal VBLP, a first NMOS transistor N
1
and a second NMOS transistor N
2
. A predetermined potential level, generally half the power supply voltage level (that is, Vcc/2), is applied to the bit line precharge voltage applying terminal VBLP. The bit line precharge control signal BLPG_
0
is commonly applied to each gate of the first and the second NMOS transistors N
1
and N
2
.
The block selection unit
40
includes a third NMOS transistor N
3
and a fourth NMOS transistor N
4
, which are coupled to the bit line pair BL
0
and /BL
0
, respectively. The bit line isolation signal BISL_
0
is commonly applied to each gate of the third and the fourth NMOS transistors N
3
and N
4
.
The equalization unit
50
includes a fifth NMOS transistor N
5
having a gate receiving the bit line equalization signal BLEQL_
0
, and a source and a drain coupled between the bit line pair BL
0
and /BL
0
.
Meanwhile, the bit line precharge control signal BLPG_
0
is a signal that is activated when the bit line pair BL
0
and /BL
0
are precharged. That is, the bit line precharge control signal BLPG_
0
is enabled from a low level to a high level when the bit line pair BL
0
and /BL
0
are precharged.
The bit line isolation signal BISL
0
is a signal that is activated to a high level in order to select a lower cell array block among a plurality of blocks. That is, the bit line isolation signal BISL_
0
maintains a predetermined level Vpp higher than the power supply voltage level Vcc at the activation operation and is set to the power supply voltage level Vcc in the precharge operation.
The bit line equalization signal BLEQL_
0
is a signal that is activated in order to equalize the bit lines to a predetermined potential level. That is, the bit line equalization signal BLEQL_
0
is enabled from a low level to a high level at the precharge operation of the bit line pair BL
0
and /BL
0
.
Referring to
FIG. 2
, the bit line precharge control signal BLPG_
0
is enabled from the low level to the high level at the precharge operation of the bit lines, so that the first and the second NMOS transistors N
1
and N
2
are turned on. In response to the first and the second NMOS transistors N
1
and N
2
being turned on, the bit line pair BL
0
and /BL
0
are set to the bit line precharge voltage (VBLP) level, which is typically half the power supply voltage level Vcc.
At this time, the bit line isolation signal BISL_
0
maintains the predetermined level Vpp higher than the power supply voltage level Vcc at the activation operation of the bit lines and is set to the power supply voltage level Vcc in the precharge operation thereof, so that the third and the fourth NMOS transistors N
3
and N
4
are maintained at a turned-on state. Also, the bit line equalization signal BLEQL_
0
is enabled from the low level to the high level in the precharge operation of the bit line pair BL
0
and /BL
0
, so that the fifth NMOS transistor N
5
is turned on.
As described above, when the bit line pair BL
0
and /BL
0
disposed at the edge portion (hereinafter, referred to as an edge bit line pair) are precharged, the first, the second and the fifth NMOS transistors N
1
, N
2
and N
5
are turned on, and the third and the fourth NMOS transistors N
3
and N
4
are maintained at a turned-on state.
FIG. 3
is a circuit diagram showing a central bit line sense amplifier and peripheral circuits, in which one bit line sense amplifier is shared with two cell array blocks. In
FIG. 3
, for the sake of convenience, only two cell array blocks (a top cell array block
10
and a bottom cell array block
11
) are illustrated.
Referring to
FIG. 3
, the central bit line sense amplifier and peripheral circuits include top and bottom cell array blocks
10
and
11
, a sense amplifier
21
, a precharge unit
31
, a top cell array block selection unit
41
a,
a top cell array block equalization unit
51
a,
a bottom cell array block selection unit
41
b
and a bottom cell array block equalization unit
51
b.
The top and the bottom cell array blocks
10
and
11
are arrayed at positions corresponding to a word line and a bit line pair, and are provided with a plurality of memory cell arrays for storing the cell data.
The sense amplifier
21
senses and amplifies the cell data through the bit line pair BL
1
and /BL
1
commonly coupled to the top and bottom cell array blocks
10
and
11
.
The precharge unit
31
precharges the bit line pair BL
1
and /BL
1
to a predetermined potential level in response to a bit line precharge control signal BLPG_
1
.
The top cell array block selection unit
41
a
controls a connection between the top cell array block
10
and the sen

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