Memory device with local write data latches

Details Memory device with local write data latches Memory device with local write data latches

1998-09-03

2001-04-17

Lane, Jack A. (Department: 2751)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C711S003000

Reexamination Certificate

active

06219283

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to a static memory device which includes latch circuitry to minimize memory array blocks.
BACKGROUND OF THE INVENTION
The performance of computer systems, especially personal computers, has improved dramatically due to the rapid growth in computer architecture design, and in particular, to the performance of computer memory. The speed with which a processor can access data is critical to its performance, while providing uniformly fast memory access can be cost prohibitive. To get around this problem, computer architectures have relied on a mix of fast, less dense, memory and slower bulk memory. In fact, many computer architectures have a multilevel memory architecture in which an attempt is made to find information in the fastest memory. If the information is not in that memory, a check is made at the next fastest memory. This process continues down through the memory hierarchy until the information sought is found. One critical component in such a memory hierarchy is a cache memory.
Cache memories rely on the principle of locality to attempt to increase the likelihood that a processor will find the information it is looking for in the cache memory. To do this, cache memories typically store contiguous blocks of data. In addition, the cache memory stores a tag which is compared to an address to determine whether the information the processor is seeking is present in the cache memory. Cache memories are usually constructed from higher speed memory devices such as static random access memory (SRAM). The typical cache memory transfers a cache line as a contiguous block of data, starting at the first word in the cache line and proceeding through to the last. Each of the bits of a cache line is typically stored in a different memory array block using one write operation. As such, numerous blocks of memory must be accessed for writing a line of data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an SRAM which can store a line of data in a single memory array block while maintaining a minimum number of input data lines.
SUMMARY OF THE INVENTION
The above mentioned problems with high speed memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. A memory is described which includes local data latches coupled to columns of a memory array.
In one embodiment, the present invention describes a static random access memory device comprising a memory array block having rows and columns of memory cells, a data communication line for receiving input data, and a plurality of local latch circuits coupled between the data communication line and the memory array block. A series of data signals received on the data communication line can be latched in the plurality of local latch circuits for writing to the memory array block in one memory write operation.
In another embodiment, static random access memory device is described which comprises a memory array block having rows and columns of memory cells, and address circuitry for receiving an externally provided memory array address and generating a series of additional memory array addresses. The externally provided memory array address and the series of additional memory array addresses form a burst address sequence. The static random access memory device further comprises a data communication input for receiving a series of input data, a plurality of local latch circuits coupled between the data communication input and the memory array block, and coupling circuitry for coupling the series of input data to the memory array block in one memory write operation after the series of input data is latched in the plurality of local latch circuits.
In another embodiment a method of operating a memory device is described. The method comprises receiving a series of data input signals, receiving an externally provided memory array start address, generating a plurality of additional memory array addresses in response to the memory array start address, sequentially activating a plurality of local latch circuits to latch a portion of the data input signals, and writing the latched portions of the data input signals to a common memory array block in one write operation.


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“2.25Mb ZBT SRAM Product Specification”,Micron Technology, Inc., (Sep 1997).
“Synchburst SRAM Product Guide”,Micron Technology, Inc., (Feb. 1998).

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