Memory device with high speed memory cell selection mechanism

Details Memory device with high speed memory cell selection mechanism Memory device with high speed memory cell selection mechanism

1979-11-16

1982-02-16

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365174, G11C 1140

Patent

active

043162657

ABSTRACT:
In a memory device, row and column decoders are connected through a common address signal line to an address buffer, and the row decoder is connected through a switch to the common address signal line. When the address buffer delivers a first address signal, the switch is turned on so that the first address signal is applied to both of the column and row decoders. The column decoder includes therein provision for disabling the column decoder when the first address signal is applied to column decoder. The column decoder therefore does not respond to the first address signal. Subsequently, when the address buffer delivers a second address signal, the switch is turned off so that the row decoder is not applied with the second address signal but the column decoder responds to the second address signal. Thus, the row and column address respond to the first and second address signals respectively.

REFERENCES:
patent: 4112508 (1978-09-01), Itoh
patent: 4208730 (1980-06-01), Dingwell et al.

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