Memory device with faster reset operation

Details Memory device with faster reset operation Memory device with faster reset operation

1999-05-10

2001-10-09

Ho, Hoal V. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S230030

Reexamination Certificate

active

06301173

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory circuit, such as a dynamic RAM (DRAM), and more particularly to a memory circuit with a faster reset operation of bit lines.
2. Description of the Related Art
An increase of capacity and speed is demanded for memory devices, such as DRAM. For example, page mode and burst mode have been proposed for increasing speed. Also recently, it is proposed to decrease the random access cycle itself, which involves changing not only column addresses but also row addresses. An example is a fast cycle RAM (FCRAM, trademark of Fujitsu, Ltd.), which has a shorter cycle time of random access operation, proposed in the Nikkei Electronics, Jun. 15, 1998 issue, pages 163-171, and in the 1998 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, pages 22-25.
FIG. 1
is a diagram depicting a circuit example of a conventional memory device. In the memory device in
FIG. 1
, a sense amplifier SA, a bit line clamper and short circuit BLR, and a column gate CLG are disposed between a first bit line pair BL
0
and /BL
0
and a second bit line pair BL
1
and /BL
1
, which are disposed in the lateral column direction. The sense amplifier SA, the bit line clamper and short circuit BLR and the column gate CLG are shared by the first and the second bit line pairs BL
0
and /BL
0
and BL
1
and /BL
1
, and are connected to the first bit line pair or the second bit line pair by conducting one of the first and second bit line transfer gates BLT
0
and BLT
1
disposed there between.
At a first and second cell matrices CM
0
and CM
1
disposed at the left and right, word lines WL
0
and WL
1
are disposed, and memory cells MC
0
and MC
1
are disposed at the cross-positions of the word lines and the bit lines. And a plurality of the circuits shown in
FIG. 1
are disposed as columns in the word line direction.
The sense amplifier SA in
FIG. 1
comprises N channel transistors N
1
, N
2
and N
3
and P channel transistors P
1
, P
2
and P
3
, and is activated when the transistor N
1
conducts responding to a sense amplifier activation signal lez at the N side, pulls down a node nsa to the ground voltage Vss, and the transistor P
1
conducts responding to a sense amplifier activation signal lex at the P side, and pulls up a node psa to the internal power supply Vii. By activation of the sense amplifier, the bit line pairs are driven and amplified to the ground voltage Vss and the internal power supply Vii.
The bit line transfer gates BLT
0
and BLT
1
comprise N channel transisters N
10
and N
11
and N
12
and N
13
respectively, and connect the corresponding bit line pair to the sense amplifier SA and the bit line clamper and the short circuit BLR under control of respective transfer control signals Blt
0
or Blt
1
.
In the bit line clamper and short circuit BLR, the N channel transistors N
4
, N
5
and N
6
conduct responding to a bit line reset signal bre, and the transistor N
4
shorts the bit line pairs, and at the same time, the transistors N
5
and N
6
clamp the bit line pairs to the precharge level Vii/2, which is ½ of the internal power supply Vii. The column gate CLG comprises N channel transistors N
14
and N
15
, which connect the bit line pairs to the data bus line pair DB and /DB responding to a column select signal c
1
.
According to the operation of the above mentioned conventional memory device, both of the bit line transfer gates BLT
0
and BLT
1
conduct in reset status, the transistors N
4
-N
6
of the bit line clamper and short circuit BLR conduct by the bit line reset signal bre, which shorts both of the bit line pairs and sets the bit line pairs to the bit line precharge level Vii/2. If the memory cell MC
0
is selected here, the bit line transfer gate BLT
1
side no longer conducts, the bit line clamper and short circuit BRL is reset so that the transistors N
4
, N
5
, N
6
are non-conductive, the word line WL
0
is driven, and a very small voltage difference is generated between the first bit line pair BL
0
and /BL
0
according to the charge stored in the memory cell MC
0
. Then the sense amplifier activation signal lez rises and lex falls, which activates the sense amplifier SA, amplifies the very small voltage difference generated between the bit line pair BL
0
and /BL
0
, and as a result one bit line is driven to the internal power supply Vii and the other bit line is driven to the ground voltage Vss. The bit line pair BL
0
and /BL
0
is connected to the data bus line pair DB and /DB responding to the column select signal c
1
, and a read signal is output via a read amplifier and an output circuit, which are not illustrated. When the word line WL
0
falls and the memory cell MC
0
is written again, the sense amplifier SA is deactivated, and at the same time, the bit line transfer gate BLT
1
side becomes conductive again, and the transistors of the bit line clamper and short circuit BLR conduct responding to the bit line reset signal bre, and short and clamp the bit line pairs BL
0
and /BL
0
and BL
1
and /BL
1
to the precharge level Vii/2.
In the configuration of the memory device shown in
FIG. 1
, the left and right bit line pairs share one sense amplifier SA, and the bit line transfer gates BLT
0
and BLT
1
connect one bit line pair to the sense amplifier SA. Also, the bit line clamper and short circuit BLR, which is a circuit for resetting the bit line, is disposed next to the sense amplifier SA, and is also shared by the left and right bit line pairs. As a consequence, this configuration is effective in terms of layout efficiency when relatively long bit line pairs are connected to one sense amplifier and when the number of rows of sense amplifier SA of the memory device is small. Because a pair of memory cell arrays CM
0
, CM
1
can share the sense amplifier row.
However, the bit line clamper and short circuit BLR is connected to the bit line pairs by way of the bit line transfer gates BLT
0
and BLT
1
, therefore the on-resistance of the transistors N
10
-N
13
of the bit line transfer gates makes the time for the reset operation of the bit line pairs long. Such a lengthy reset operation time makes the cycle time of the random access operation longer.
FIG. 2
is a diagram depicting another circuit example of a conventional memory device. The same numerals as in
FIG. 1
are used in
FIG. 2
if the parts are the same. In the example of prior art in
FIG. 2
, the left and right bit line pairs BL
0
and /BL
0
and BL
1
and /BL
1
disposed in the column direction, share the sense amplifier SA, just like the first example of prior art. Therefore, the bit line transfer gates BLT
0
and BLT
1
are disposed between the sense amplifier SA and each bit line pair respectively. As with the sense amplifier SA, the column gate CLG is also shared by both bit line pairs.
In the example of prior art shown in
FIG. 2
, the bit line clamper and short circuit BLR, which is a bit line reset circuit, is disposed for each bit line pair in order to increase the speed of operation to short and reset the bit line pairs to the precharge level Vii/2. In other words, the bit line clamper and short circuit BLR
0
is connected to the right bit line pair BL
0
and /BL
0
, shorts the connected bit line pair BL
0
and /BL
0
responding to the reset signal blt
1
, and clamps the bit line pair to the precharge level Vii/2. In the same way, the bit line clamper and short circuit BLR
1
is connected to the left bit line pair BL
1
and /BL
1
, shorts the connected bit line pair BL
1
and /BL
1
responding to the reset signal blt
0
, and clamps the bit line pair to the precharge level Vii/2. The respective bit line clamper and short circuit BLR
0
, BLR
1
comprises N channel transistors for shorting N
4
and N
24
, and N channel transistors for clamping N
5
and N
6
, and N
25
and N
26
in the same way.
In the case of the example of prior art shown in
FIG. 2
, the same control signal blt
1
controls the right bit line clamper and short circuit BLR
0
and the left bit line transfer gate BLT
1
, and the s

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