Memory device with fast word-line-discharging-circuits

Details Memory device with fast word-line-discharging-circuits Memory device with fast word-line-discharging-circuits

1980-12-18

1982-12-28

Martin, John C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365155, 365233, G11C 702, G11C 1140, G11C 802

Patent

active

043665586

ABSTRACT:
In a memory comprising an upper word line and a lower word line for selecting memory cells connected therebetween, a delay circuit connected to the upper word line provides a first signal having a predetermined level when a voltage applied to the upper word line is between a selection voltage and a predetermined voltage, and a second signal, which is a delayed signal of the upper word line voltage signal, when the upper word line voltage changes from the predetermined voltage toward the non-selection voltage. The output of the delay circuit is used to control a switch circuit for discharging the lower word line therethrough.

REFERENCES:
patent: 4156941 (1979-05-01), Homma et al.

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