Memory device with end of cycle precharge utilizing write signal

Details Memory device with end of cycle precharge utilizing write signal Memory device with end of cycle precharge utilizing write signal

1993-10-04

1995-04-04

Gossage, Glenn

Static information storage and retrieval

Read/write circuit

Precharge

365194, 365233, 3652335, G11C 11407, G11C 11417

Patent

active

054043271

ABSTRACT:
A memory device (10) having a precharge and timing control circuit (24) is configured so that a precharge state occurs at the end of memory cycles. A precharge signal remains active until a change of address is detected by an address transition detector (14). This address change causes a word line controller (86) to activate memory word lines (20), a precharge controller (82) to deactivate the precharge signal, and a sense amp latch controller (88) to enable sense amplifiers within a write and sense amplifier control circuit (38). After a sufficient amount of time has transpired for either a write operation to occur or for valid data to be detected in the sensing amplifiers, the word line controller (86) deactivates the word lines (20), the sense amp latch controller (88) latches the sense amplifiers, and the precharge controller (82) activates the precharge signal. During a read memory cycle, the precharge signal is active while valid data propagates through output stages (38, 18, 40) of the memory device (10). During a write memory cycle, write control signal or data signal transitions are detected to control the precharge signal.

REFERENCES:
patent: 4337525 (1982-06-01), Akatsuka
patent: 4592026 (1986-05-01), Matsukawa et al.
patent: 4612631 (1986-09-01), Ochii
patent: 4625298 (1986-11-01), Sumi
patent: 4638462 (1987-01-01), Rajeevakumar et al.
patent: 4712194 (1987-12-01), Yamaguchi et al.
patent: 4744063 (1988-05-01), Ohtani et al.

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