Memory device with barrier portions having defined capacitance

Details Memory device with barrier portions having defined capacitance Memory device with barrier portions having defined capacitance

1998-12-08

2001-11-20

Whitehead, Jr., Carl (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S017000, C257S023000, C257S021000, C257S025000, C257S014000, C257S009000, C029S030000, C029S028000

Reexamination Certificate

active

06320216

ABSTRACT:

This patent claims priority benefits to prior Japan application number P09-339051 dated Dec. 9, 1997.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device for recording information by accumulating charges, and a memory array formed by integrating the memory devices.
2. Description of the Related Art
A conventional memory device represented by an EEPROM (Electrically Erasable and Programmable Read Only Memory) or a flash memory has a charge accumulation layer for accumulating charges (i.e., electrons or holes) surrounded by an insulating film such as a SiO
2
(silicon dioxide) film between a gate electrode and a substrate of a MOS (Metal-Oxide-Semiconductor) transistor. In the memory device, when a high voltage is applied between a source electrode and a drain electrode thereof and a high voltage is applied to the gate electrode, charges are conducted through the insulating film according to tunnel effect and accumulated in the charge accumulation layer and a difference in the number of charges accumulated is retained as a difference in information. The retained information can be read out by using the fact that the magnitude of a current flowing between the source electrode and the drain electrode changes according to the number of charges accumulated in the charge accumulation layer.
In the conventional memory device, however, the charge accumulation layer is surrounded by an insulating film of a single layer. For making the information retaining time sufficiently long, therefore, the insulating film has to be made thick so as to have a thickness in the range of, for example, approximately 10 to 20 nm. For writing and erasing information practically, therefore, a large gate voltage of at least 10 V has to be applied, which results in hindering implementation of finer devices.
Furthermore, in the conventional memory device, whereas a large gate voltage has to be applied for writing or erasing information, even a small gate voltage causes some charge conduction and changes the number of charges accumulated in the charge accumulation layer. In a memory array formed by integrating a plurality of memory devices, therefore, the following problem also occurs: even if writing and reading information are conducted for one memory device, some charge conduction also occurs in memory devices located in the vicinity thereof, and consequently retained information is disturbed.
SUMMARY AND OBJECT OF THE INVENTION
In view of the above described problems, the present invention has been made. An object of the present invention is to provide a memory device which can conduct writing and erasing information at high speed and with a low gate voltage, perform high integration with reduced power dissipation, and retain information accurately, and to provide a memory array formed by integrating the memory devices.
A memory device according to the present invention includes a conduction layer serving as a current passage, a charge accumulation layer for accumulating charges transited from the conduction layer, one or more transition layers for transiting charges from the conduction layer to the charge accumulation layer being formed between the charge accumulation layer and the conduction layer, and a plurality of barrier portions each having a capacitance smaller than e
2
/k
B
T (where e is the electric prime quantity, k
B
is the Boltzmann's constant, and T is operation temperature) being respectively formed between one of the transition layers and the conduction layer, between the transition layers, and one of the transition layers and the charge accumulation layer.
Another memory device according to the present invention includes a conduction layer serving as a current passage, and a coupled quantum box layer formed so as to be adjacent to the conduction layer. Each capacitance of a barrier layer located between the conduction layer and a quantum box layer and barrier layers located in between each quantum box layer are smaller than e
2
/k
B
T (where e is the electric prime quantity, k
B
is Boltzmann's constant, and T is operation temperature).
A memory array according to the present invention is obtained by integrating the memory devices of the present invention.
In the memory device according to the present invention, when a voltage is applied between the conduction layer and the charge accumulation layer in a forward direction, charges in the conduction layer transit to the charge accumulation layer via the transition layers. Thereby, charges are accumulated in the charge accumulation layer, and information is retained. This information can be read out since the value of a current flowing through the conduction layer varies depending on whether charges are accumulated in the charge accumulation layer or not. Also when a voltage is applied between the conduction layer and the charge accumulation layer in a reverse direction, the charges accumulated in the charge accumulation layer transit to the conduction layer via the transition layers. Thereby, the information is erased. Since the transition of charges between the conduction layer and the charge accumulation layer is conducted via the transition layers, writing and erasing information can be conducted at high speed and with low power. Furthermore, since the barrier portion has a capacitance smaller than e
2
/k
B
T, the charge transition between the conduction layer and the charge accumulation layer does not occur even if a voltage in a predetermined range is applied. In other words, if a voltage having a magnitude exceeding the predetermined range is applied, charges transit from the conduction layer to the charge accumulation layer or from the charge accumulation layer to the conduction layer.
In another memory device according to the present invention, when a voltage is applied between the conduction layer and the coupled quantum box layer in a forward direction, charges transit in the conduction layer to the coupled quantum box layer. Thereby, information is retained. This information can be read out since the value of a current flowing through the conduction layer varies depending on whether charges are accumulated in the coupled quantum box layer or not. Also, when a voltage is applied between the conduction layer and the coupled quantum box layer in a reverse direction, the charges accumulated in the charge accumulation layer transit to the conduction layer. Thereby, the information is erased. Since the coupled quantum box layer is used, the charge transition between the conduction layer and the coupled quantum box layer is caused by resonance tunneling and writing and erasing information are conducted at high speed and with low power. Furthermore, since the barrier layer in the coupled quantum box layer has a capacitance smaller than e
2
/k
B
T, the charge transition between the conduction layer and the coupled quantum box layer does not occur even if a voltage in a predetermined range is applied. In other words, if a voltage having a magnitude exceeding the predetermined range is applied, charges transit from the conduction layer to the coupled quantum box layer or from the coupled quantum box layer to the conduction layer.
A memory array according to the present invention uses the memory devices of the present invention. By applying a voltage above or below a predetermined value between the conduction layer and the charge accumulation layer or between the conduction layer and the coupled quantum box layer of a specific memory device, information is written or erased.


REFERENCES:
patent: 5701017 (1997-12-01), Patel
patent: 5719404 (1998-02-01), Ugajin
patent: 5886380 (1999-03-01), Nakajima
patent: 6133603 (2000-10-01), Nomoto
patent: 0569840A1 (1993-05-01), None

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