Memory device with an asymmetric layout structure

Details Memory device with an asymmetric layout structure Memory device with an asymmetric layout structure

2011-01-11

2011-01-11

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S051000, C257S368000, C257S388000, C257S412000

Reexamination Certificate

active

07869262

ABSTRACT:
An SRAM device includes a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line; and a second pass gate transistor connecting the second inverter to a complementary bit line, wherein the first or second pass gate transistor has a layout structure where a first distance between its gate conductive layer and its source contact is purposefully designed to be substantially different from a second distance between its gate conductive layer and its drain contact for reducing leakage current induced by misalignment of the gate conductive layer with respect to the source contact.

REFERENCES:
patent: 7279755 (2007-10-01), Lee et al.
patent: 7521715 (2009-04-01), Jang et al.
patent: 2005/0111251 (2005-05-01), Liaw
patent: 2007/0090428 (2007-04-01), Liaw
patent: 2007/0241411 (2007-10-01), Yang et al.

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