Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-08-16
2002-08-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080, C336S082000, C336S083000
Reexamination Certificate
active
06434057
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a memory device with an output buffer. More specifically, the present invention discloses an output buffer with an output signal that is generated from a sense amplifier.
2. Description of the Prior Art
Please refer to FIG.
1
and FIG.
2
.
FIG. 1
is a diagram of a memory circuit
10
according to the prior art.
FIG. 2
is a diagram of a memory array
12
as shown in FIG.
1
. The memory circuit
10
comprises a memory array
12
, an address buffer
14
, a row decoder
16
, a column decoder
18
, a sense amplifier
22
, and an output buffer
28
. The memory array
12
comprises a plurality of word lines
32
, a plurality of bit lines
34
and a plurality of memory cells
36
. Each of the memory cells
36
is coupled to a corresponding word line
32
and a corresponding bit line
34
, and is used for storing one binary bit of data.
When data stored in one of the memory cells
36
is to be accessed, a corresponding address signal ADRS is transmitted to the memory circuit
10
, and the memory circuit
10
then outputs a corresponding data output signal Dout. The address buffer
14
transforms the address signal ADRS, transmitted from an input terminal of the memory circuit
10
, into two address signals AX and AY. The address signals AX and AY are then sent to the row decoder
16
and the column decoder
18
, respectively. The row decoder
16
selects a corresponding word line
32
according to the address signal AX, and the column decoder
18
selects a corresponding bit line
34
according to the address signal AY. In this manner, the memory cell
36
corresponding to the address signal ADRS outputs a corresponding data signal to the sense amplifier
22
according to the data stored within this cell
36
. The sense amplifier
22
amplifies the data signal outputted from the memory cell
36
to determine if the data stored in the memory cell
36
is a binary “1” or “0”, and thereby generates an output signal SA/SAB. The output signal SA/SAB comprises two complementary voltage signals SA and SAB. When the voltage signal SA is a high voltage, the voltage signal SAB is a low voltage, and vice versa, when the voltage signal SA is a low voltage, then the voltage signal SAB is a high voltage. The output signal SA/SAB is transmitted from a data output port
38
of the sense amplifier
22
to the output buffer
28
, which has a control terminal
42
for accepting a control signal OE. When the control signal OE is high, the output buffer
28
amplifies the output signal SA/SAB to generate the data output signal Dout, and when the control signal OE is low, the output buffer
28
does not amplify the output signal SA/SAB.
While the represented data of the output signal SA/SAB is in an undefined state, the memory circuit
10
utilizes an address transition detector (ATD)
24
and a delay circuit
26
for producing the control signal OE so as to control the output of the output buffer, thus preventing an undefined output signal SA/SAB from being amplified by the output buffer
28
, which could otherwise adversely affect the accuracy of the data output signal Dout. The address transition detector
24
is used to detect variations of the address signals AX and AY to generate a control signal ADT. The delay circuit
26
is used to delay the control signal ADT for a predetermined time interval, and the signal outputted from the delay circuit
26
is the control signal OE.
Please refer to
FIG. 3
, which is a timing diagram of signals generated in the memory circuit
10
. The output signal SA/SAB is represented, respectively, by two complementary voltage signals SA and SAB. Data outputted from the memory cell
36
is a “1” when the voltage signal SA is greater than a first predetermined high voltage VH
1
and the voltage signal SAB is smaller than a first predetermined low voltage VL
1
(an interval T
2
as shown in FIG.
3
). The data outputted from the memory cell
36
is a “0” when the voltage signal SA is smaller than the first predetermined low voltage VL
1
and the voltage signal SAB is greater than the first predetermined high voltage VH
1
(an interval T
4
as shown in FIG.
3
). The data outputted from the memory cell
36
is undefined when any one of the voltage signals SA or SAB is between the first predetermined high voltage VH
1
and the first predetermined low voltage VL
1
(intervals T
1
and T
3
as shown in FIG.
3
).
As shown in
FIG. 3
, when the control signal OE rises from a second predetermined low voltage VL
2
to a second predetermined high voltage VH
2
, the output buffer
28
amplifies the output signal SA/SAB and generates the data output signal Dout. When the control signal OE drops from the second predetermined high voltage VH
2
to the second predetermined low voltage VL
2
, the output buffer
28
stops amplifying the output signal SA/SAB. The amplitude of the data output signal Dout varies between a third predetermined high voltage VH
3
and a third predetermined low voltage VL
3
, and the outputted data of the memory circuit
10
is a “1” or a “0” according to the amplitude of the output signal Dout, which is output from the output buffer
28
. When the amplitude of the output signal Dout equals the third predetermined high voltage VH
3
, the outputted data is a “1”. When the amplitude of the output signal Dout equals the third predetermined low voltage VL
3
, the outputted data is a “0”. When the control signal OE drops from the second predetermined high voltage VH
2
to the second predetermined low voltage VL
2
, i.e., when the output buffer
28
stops amplifying the output signal SA/SAB, the amplitude of the output signal Dout will be a middle voltage VM regardless of whether the amplitude of the output signal Dout should be equal to the predetermined third high voltage VH
3
or the predetermined third low voltage VL
3
. The middle voltage VM is approximately equal to the average of VH
3
and VL
3
, i.e, VM (VH
3
+VL
3
)/2.
Although the desired time interval of the delayed control signal ATD from the delay circuit
26
is determined before manufacturing the memory circuit
10
, the actual delay time interval of the delay circuit
26
varies with an operating temperature of the memory circuit
10
, or due to manufacturing processes of the memory circuit
10
. When the variation of the delayed time interval exceeds a predetermined range, the speed and accuracy of the memory circuit
10
will be affected. If the delayed time interval of the delay circuit
26
is longer, the accessing speed of the memory circuit
10
is reduced. As shown in
FIG. 3
, when the represented data of the output signal SA/SAB has confirmed and past a predetermined time interval Tout, the control signal OE rises to the second predetermined high voltage VH
2
, and the output buffer
28
begins amplifying the output signal SA/SAB. When the delayed time interval of the delay circuit
26
is longer, the predetermined time interval Tout is also longer, so the accessing time interval of the memory circuit
10
is longer, which causes the accessing speed to become slower. On the other hand, when the delayed time interval of the delay circuit
26
is shorter, the accessing speed of the memory circuit
10
becomes faster. However, the memory circuit
10
will more easily generate errors during the data accessing process if the delayed time interval of the delay circuit
26
is too short.
Please refer to
FIG. 4
, which is a timing diagram of signals generated in the memory circuit
10
when a data accessing error occurs. As shown in
FIG. 4
, when the presented data of the output signal SA/SAB is undefined, that is, when any one of the voltage signals SA or SAB is between the first predetermined high voltage VH
1
and the first predetermined low voltage VL
1
, the control signal OE rises from the second predetermined low voltage VL
2
to the second predetermined high voltage VH
2
. In the data translation process of the output signal SA/SAB from a “0” to a “1” (an interval T
5
as shown in FIG.
4
), at a t
Chen Jui-Lung
Huang Shih-Huang
Auduong Gene N.
Hsu Winston
Nelms David
United Microelectronics Corp.
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