Memory device with a data hold latch

Details Memory device with a data hold latch Memory device with a data hold latch

2008-03-25

2008-03-25

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189011, C365S189040, C365S206000

Reexamination Certificate

active

10865274

ABSTRACT:
A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

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U.S. Appl. No. 10/412,490, filed Apr. 11, 2003.

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