Memory device wherein a shadow register corresponds to each memo

Details Memory device wherein a shadow register corresponds to each memo Memory device wherein a shadow register corresponds to each memo

1988-10-28

1990-09-04

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Multiplexing

365 78, G11C 1900

Patent

active

049549880

ABSTRACT:
A data storage device includes two registers associated with each cell of the memory. The first register forms a read/write memory register, and the second register forms a write-only shadow register connected to the memory register. During normal operations, each memory register operates as an independent random access memory (RAM) cell and each shadow register operates as an independent write-only RAM cell. When data is written to a shadow register, a flag bit is set. Subsequently, a validity check may be performed to verify the data. If the data does not verify, a clear line may be used to clear the flag bits. If the data verifies, the data in each shadow register with a flag bit set can be loaded into its corresponding memory register in a gang loading operation. If a shadow register flag bit is not set, the data in its corresponding memory register is not changed during gang loading.

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