Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-08-04
2008-10-28
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S005110, C714S042000, C714S054000, C714S718000, C714S721000, C714S723000, C714S730000, C711S106000, C365S201000, C365S225700
Reexamination Certificate
active
07444577
ABSTRACT:
A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.
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Best Scott C.
Tsern Ely K.
RAMBUS Inc.
Shemwell Mahamedi LLP
Trimmings John P
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