Memory device structure and method of fabricating the same

Details Memory device structure and method of fabricating the same Memory device structure and method of fabricating the same

2002-07-09

2003-11-04

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

06642111

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to a semiconductor device structure and the method of fabricating the same. More particularly, this invention relates to a memory device structure and the method of fabricating the same.
2. Background of the Invention
Typical flash memory cells use poly-silicon to form the floating gate. During programming, the electrons injected into the floating gate are distributed uniformly on the whole layer of the floating gate. However, when the tunnel oxide under the poly-silicon floating gate has defects, the device tends to have leakage current, resulting in reliability issues.
Thus, a memory device has been developed which has a structure of Silicon-Oxide-Nitride-Oxide-Semiconductor (SONOS). When the voltage between the word line and the buried drain is being programmed, the electrons in the channel and close to the buried drain region are injected into the silicon nitride layer. Since silicon nitride has a special property of catching electrons, the injected electrons do not distribute uniformly on the whole silicon nitride layer. They rather crowd and localize on the silicon nitride layer with a Gauss″s distribution. Because the electrons injected into the silicon nitride layer only distribute in a local region, the device is then not as sensitive to the defects of the tunnel oxide. As a result, it performs better with less leakage current.
FIG. 1A
to
FIG. 1C
are cross-section process flow diagrams of an existing SONOS memory device.
Referring to
FIG. 1A
, a substrate
100
is provided first, where the substrate
100
has a memory cell region
120
and a periphery circuit region
130
. Further, an oxide layer
102
is formed on the substrate
100
. Afterwards, a silicon nitride layer
104
and an oxide layer
106
are formed on the oxide layer
102
, and then the oxide layer
102
, the silicon nitride layer
104
and the oxide layer
106
belonged to the periphery circuit region
130
are etched. A gate oxide layer
103
of the periphery circuit region
130
is grown by the wet oxidation method, without being grown in the memory cell region at this time. Then, at the same time, a poly silicon layer
108
is formed on top of the silicon oxide layer
106
in the memory cell region
120
and also on top of the oxide layer
103
in the region of the periphery circuit
130
. A photo resist layer
110
is then patterned on top of the poly-silicon layer
108
, covering the area where the gate structure is to be formed.
Referring to
FIG. 1B
, using the photo resist layer
110
as an etch mask, the stack of layers in the memory cell region
102
including the poly silicon layer
108
, the silicon oxide layer
106
, the silicon nitride layer
104
and the silicon oxide layer
102
, as well as the stack in the periphery circuit region
130
including the poly silicon
108
and the silicon oxide
103
, are patterned to form a gate structure in each of the two regions
120
,
130
respectively. In the memory cell region
120
, the formed gate structure comprises a tunnel oxide layer
102
b
, a silicon nitride electron-capturing layer
104
b
, a barrier oxide layer
106
b
and a poly-silicon layer
108
b
. In the periphery circuit region
130
, on the other hand, the formed gate structure comprises a gate oxide layer
103
a
and a poly-silicon layer
108
a
. Further, the gate structures are used to be masks during the ion implantation forming the lightly doped drain regions
112
b
,
112
a
in the substrate
100
around the gate structures in regions
120
and
130
, respectively.
Following that, referring to
FIG. 1C
, spacer walls
114
b
,
114
a
are formed surrounding the gate structures in the memory region
120
and the periphery circuit region
130
, respectively. The spacer walls
114
b
,
114
a
are then used as another mask of implantation to form the source and drain regions
116
b
,
116
a
in the substrate
100
, surrounding the spacer walls
114
b
,
114
a
. After this, one can precede with the metal wire layers and other backend processes to complete the memory processing.
In the above stated process steps of fabricating the memory device, the patterning of the poly-silicon is etched in one step for both memory region and periphery region, and following the poly-silicon etch is the etch for the oxide-nitride-oxide (O—N—O) layer in the memory region and the etch for the gate oxide in the periphery circuit region. However, due to the big difference between the thickness and structures of O—N—O layer in the memory region and that of the gate oxide layer in the periphery circuit region, and provided that the gate oxide thickness is getting thinner and thinner for the 0.25 &mgr;m process and under, it is difficult to control the etching to completely etch through the O—N—O structure without lowering (or pitting) the substrate surface in the periphery circuit region by over-etching the gate oxide. In order to solve the above process issue, another existing method is separating the poly-silicon etch step into two steps for the periphery circuit region and the memory region, insuring the completeness of the device. However, this method must use one additional photolithography mask, thus adding process complexity.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention is to provide a SONOS memory device structure and its fabrication method, so as to solve the problem of having damaged substrate surface in the periphery circuit region during poly-silicon etch.
It is another object of the invention to provide a memory device structure and its fabrication method, so as to reduce process complexity.
The invention provides a method of fabricating a memory device. The method includes the following steps. First, from the substrate and up, a tunnel oxide layer, a silicon nitride layer and a barrier silicon oxide layer are formed consecutively. A conductive layer is formed right on top of the last silicon oxide layer. This conductive layer is then patterned, and, at the same time the silicon oxide layer is also patterned, exposing the silicon nitride layer. Following that, a blanket dielectric layer is formed on top, covering the gate layer and the silicon nitride layer. This dielectric layer is then defined by using one etch step to form a spacer wall on the sides of the gate layer. During this etch step, the silicon nitride layer not covered by the spacer wall can be advantageously etched away and form the silicon nitride electron capturing layer. Note that the width of the formed electron-capturing layer is larger than that of the conductive gate layer. The current invention also includes forming a source/drain area in the substrate around the spacer, and forming a silicide layer on top of the gate layer to reduce the gate contact resistance.
The invention provides a method of fabricating a memory device. The method includes the following steps. First, a substrate is provided which has a memory region and a periphery circuit region. Secondly, an oxide layer is formed on the surface of the substrate, and a silicon nitride layer and another dielectric layer are formed on top of the oxide layer at only the memory region. After that, a conductive layer is formed on top of the dielectric layer at the memory region and the oxide layer at the periphery circuit region. This conductive layer is then patterned to form a first gate at the memory region and a second gate at the periphery circuit region. During this patterning step, the dielectric layer at the memory region and the oxide layer at the periphery circuit region are also patterned in the same step, exposing the silicon nitride layer in the memory region. A blanket dielectric layer is then formed on top, covering the first gate, the silicon nitride layer, and the second gate in both regions. Following that, an etch step is used to pattern the blanket dielectric layer and form a spacer on the sidewall of the first gate, and form another spacer on the sidewall of the second gate. During this patterning step, the silicon nitride layer in the memory re

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