Memory device resistant to soft errors

Details Memory device resistant to soft errors Memory device resistant to soft errors

1983-12-23

1986-05-27

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365190, 365230, G11C 700, G11C 1140

Patent

active

045920265

ABSTRACT:
In a memory device, a plurality of memory cells are connected to bit line pairs. A precharge circuit is controlled by a chip enable signal during a stand-by state and by an address transition detector signal during an active state, to charge the bit line pairs up to a given power source voltage.

REFERENCES:
patent: 4069475 (1978-01-01), Boettcher
patent: 4150441 (1979-04-01), Ando
patent: 4161040 (1979-07-01), Satoh
patent: 4355377 (1982-10-01), Sud et al.
patent: 4417328 (1983-11-01), Ochii
Watanabe et al., "A Battery Backup 64K CMOS RAM with Double Level Aluminum Technology," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 60-61, Feb. 23, 1983.

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