Memory device protected against undesirable supply voltage level

Details Memory device protected against undesirable supply voltage level Memory device protected against undesirable supply voltage level

1980-02-07

1981-09-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365229, 3072382, G11C 1140

Patent

active

042901197

ABSTRACT:
A memory circuit includes memory cells and access circuit for accessing to desired memory cells. The access circuit is driven by a driver which includes an emitter coupled logic for providing a switch-on signal of a low level in response to an input signal. A switch circuit in the driver provides the access circuit with a drive signal of a low level in response to the switch on signal. The driver further includes a control circuit for clamping the output of the emitter coupled logic to a non-drive signal of a high level when supply voltages does not satisfy predetermined conditions.

REFERENCES:
patent: 4085311 (1978-04-01), Ohasako et al.
patent: 4227257 (1980-10-01), Sato

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