Memory device performing write leveling operation

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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C365S189020

Reexamination Certificate

active

07929355

ABSTRACT:
A memory device includes a multiplexing unit, a pipe latch unit, and an output driver. The multiplexing unit outputs data input from global input/output lines in a normal mode and outputs write leveling data in a writing leveling mode being entered in response to a write leveling signal. The pipe latch unit latches the data outputted from the multiplexing unit and outputting the latched data. The output driver outputs the latched data outputted from the pipe latch unit.

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patent: 6816416 (2004-11-01), Won
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patent: 2008/0304336 (2008-12-01), Kim et al.
patent: 2005-038526 (2005-02-01), None
patent: 10-0521047 (2005-10-01), None

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