Memory device outputting read data in a time starting from a...

Details Memory device outputting read data in a time starting from a... Memory device outputting read data in a time starting from a...

2006-01-24

2006-01-24

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C327S263000, C365S194000

Reexamination Certificate

active

06990596

ABSTRACT:
The memory device of the invention outputs the read data in a time starting from the rising edge of the external clock that is shorter than that of other known devices, because the output buffer has an array of master-slave pairs of flip-flops synchronized by respective timing signals derived from the internal clock signal. The array receives data from the state machine through the second internal bus and provides the data to be output to the output stage of the buffer enabled by the state machine. A logic circuit generates timing signals for the master-slave flip-flops, respectively as logic NAND and logic AND of the internal clock signal and of an enabling signal of the output stage of the buffer generated by the state machine. Moreover, the memory device includes a circuit, synchronized by the internal clock signal, that introduces a delay of the enabling signal of the output stage of the buffer equivalent to a period of the internal clock signal.

REFERENCES:
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patent: 6094380 (2000-07-01), Kim
patent: 6169435 (2001-01-01), Fujii et al.
patent: 6426900 (2002-07-01), Maruyama et al.
patent: 6763444 (2004-07-01), Thomann et al.
patent: 2000057771 (2000-02-01), None
patent: 99/15971 (1999-04-01), None

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