Memory device, memory device read method

Details Memory device, memory device read method Memory device, memory device read method

2006-06-20

2006-06-20

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S189050

Reexamination Certificate

active

07065002

ABSTRACT:
A memory device that amplifiers read data based on the timing of a CLK signal input from an external device comprises: a delay circuit5that controls a code of the CLK signal and a delay amount based on a CT signal input from an external device to output a CLK_delay signal; a sense enable signal generation section6that generates a sense enable signal based on the CLK_delay signal; a memory cell4that outputs data in accordance with an instruction from outside; and a sense amplifier7that amplifiers the output of the memory cell in accordance with the sense enable signal.

REFERENCES:
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patent: 5812492 (1998-09-01), Yamauchi et al.
patent: 6192003 (2001-02-01), Ohta et al.
patent: 6236253 (2001-05-01), Leasure et al.
patent: 9-320261 (1997-12-01), None
patent: 2000-163966 (2000-06-01), None

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