Memory device having shared open bit line sense amplifier...

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

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C365S207000

Reexamination Certificate

active

07317646

ABSTRACT:
Provided is a memory device with a shared open bit line sense amplifier architecture. The memory device includes memory cell arrays, each memory cell array including bit lines, and a sense amplifier configured to couple to at least two bit lines a memory cell array and configured to couple to at least two bit lines of a different memory cell array.

REFERENCES:
patent: 4888732 (1989-12-01), Inoue et al.
patent: 5016224 (1991-05-01), Tanaka et al.
patent: 6914837 (2005-07-01), Schroeder et al.
patent: 07-254650 (1995-10-01), None
patent: 11-053881 (1999-02-01), None
patent: 2002-289815 (2002-10-01), None
English language abstract of Japanese Publication 07-254650.
English language abstract of Japanese Publication 11-053881.
English language abstract of Japanese Publication 2002-289815.

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