Memory device having selectable number of output pins

Details Memory device having selectable number of output pins Memory device having selectable number of output pins

1991-07-12

1993-11-16

Grimm, Siegfried H.

Static information storage and retrieval

Read/write circuit

Multiplexing

36518903, G06F 1300, G11C 700

Patent

active

052629902

ABSTRACT:
A memory device includes a memory array and a plurality of output pins. A control input is provided for receiving a control signal. The control signal can be in a first voltage state and a second voltage state. When the control signal is in the first voltage state, the memory device is in a first output mode. When the control signal is in the second voltage state, the memory device is in a second output mode. Circuitry is provided for selectively coupling the plurality of output pins to the memory array. An output mode select logic is coupled to receive the control signal for selecting the first output mode and the second output mode for the memory device. When the memory device is in the first output mode, the output mode select logic controls the circuitry to couple all of the plurality of output pins to the memory array. When the memory device is in the second output mode, the output mode select logic controls the circuitry to couple a portion of the plurality of output pins to the memory array. A method of controlling the memory device to switch between the first output mode and the second output mode is also described.

REFERENCES:
patent: 4907203 (1990-03-01), Wada et al.
patent: 5091851 (1992-02-01), Shelton et al.

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