Memory device having redundancy fuse blocks arranged for...

Details Memory device having redundancy fuse blocks arranged for... Memory device having redundancy fuse blocks arranged for...

2006-12-01

2008-10-28

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having fuse element

C365S200000, C365S063000

Reexamination Certificate

active

07443756

ABSTRACT:
A method of arranging redundancy fuse block arrays may reduce test time for a memory device. The memory device may include a stack bank structure in which at least two banks share a row decoder or a column decoder. Redundancy fuse block arrays for the two banks may be alternately arranged in an X-axis direction or a Y-axis direction of a wafer. Accordingly, a tester may repair defective rows or columns of the two banks without shifting from one axis.

REFERENCES:
patent: 5636172 (1997-06-01), Prall et al.
patent: 6314032 (2001-11-01), Takase
patent: 6388941 (2002-05-01), Otori et al.
patent: 6407950 (2002-06-01), Ooishi
patent: 6834016 (2004-12-01), Kato et al.
patent: 2005/0002243 (2005-01-01), Mohr et al.
patent: 2006/0039210 (2006-02-01), Blodgett
patent: 1999-000470 (1999-01-01), None
English language abstract for Korean Publication No. 1999-000470.

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