Memory device having open bit line architecture for...

Details Memory device having open bit line architecture for... Memory device having open bit line architecture for...

2007-12-25

2007-12-25

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S210130, C365S230030, C365S063000

Reexamination Certificate

active

11260760

ABSTRACT:
In a memory device having an open bit line architecture for improving repairability and a method of repairing the memory device, redundant memory cells used to repair defective cells are included even in first and second edge sub-arrays that are arranged at the edges of a memory array. Further, memory cells connected to some of the bit lines in a normal sub-array can be replaced with redundant memory cells included in the first edge sub-array, and memory cells connected to the remaining bit lines can be replaced with redundant memory cells included in the second edge sub-array. Therefore, in the memory device having an open bit line architecture according to the present invention, if all of the redundant memory cells included in normal sub-arrays have been exhausted through replacement, defective cells can be repaired using the redundant memory cells included in the edge sub-arrays. Therefore, the memory device and method of repairing the memory device according to the present invention are advantageous in that they can remarkably improve repairability.

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patent: 10-0161729 (1998-08-01), None
patent: 10-2000-0051869 (2000-08-01), None

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