Memory device having latch for charging or discharging data...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S189080, C365S230080

Reexamination Certificate

active

08050110

ABSTRACT:
A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.

REFERENCES:
patent: 5808490 (1998-09-01), Watanabe
patent: 6307791 (2001-10-01), Otsuka et al.
patent: 6489807 (2002-12-01), Genna et al.
patent: 7266747 (2007-09-01), Foss
patent: 2005/0135158 (2005-06-01), Park
patent: 2005/0157532 (2005-07-01), Yamamura
patent: 2006/0104127 (2006-05-01), Cha et al.
patent: 1637932 (2005-07-01), None
Search Report issued from Taiwanese Intellectual Property Office on Jan. 25, 2011.
Patent Certificate issued from State Intellectual Property Office of the P.R.C on May 4, 2011.

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