Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-06-16
2001-09-04
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S208000
Reexamination Certificate
active
06285611
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices such as synchronous DRAMs and to input/output (IO) sense amplifiers that require less area in a semiconductor memory.
2. Description of the Related Art
Synchronous DRAMs (dynamic random access memories) improve the operational speed by operating a data pipeline in synchronization with a system clock signal. Accordingly, synchronous DRAMs can receive and input the address for a next memory access while current data is being processed and output. The synchronous DRAMs constantly output data from a plurality of banks and are thus faster than conventional DRAMs, which have idle time between receipt of an address and output of data.
To maintain the continuous output of data, each bank of a conventional synchronous DRAM has separate data lines and IO sense amplifiers. For example, an SDRAM with a 16-bit data width requires 16 data lines and 16 IO sense amplifiers per bank. Assuming that a memory device has four memory banks, the memory device requires 64 (4×16) IO sense amplifiers.
Recent development of multi-media technology has increased the demand for semiconductor memory devices having larger data widths. Accordingly, semiconductor memory devices having a large data width including memories with 32-bit or 64-bit data widths are being developed. This increase in the data width means an increase in the number of data lines and IO sense amplifiers, which directly causes an increase in the chip area. The larger chip area can decrease the number of semiconductor memory devices produced per wafer and can correspondingly increase the costs of the memory devices.
SUMMARY OF THE INVENTION
To solve the above problems, the present invention provides a semiconductor memory device in which IO sense amplifiers occupy less integrated circuit area. In one embodiment of the invention, a memory device includes a plurality of memory banks, a plurality of data line pairs connect to the memory banks, and an input/output (IO) sense amplifier that at least two neighboring memory banks share. The IO sense amplifier selectively amplifies or senses data signals on the data lines of one of the at least two memory banks. The sharing of IO sense amplifiers means that the total circuit area that sense amplifiers occupy in a memory device is less than the circuit area that would be required if each bank had a separate IO sense amplifier.
In one particular embodiment, the IO sense amplifier includes a latch sense amplifier and at least two current sense amplifiers. Each current sense amplifier connects to a data line pair of a corresponding one of the at least two memory banks and senses differences in currents flowing through the connected data lines. An output voltage from each current sense amplifier indicates a result of the current sensing. The latch sense amplifier connects to the at least two current sense amplifiers, for sensing the output voltage from a selected one of the current sense amplifiers. The latch sense amplifier amplifies the sensed output voltage to a level that is enough for transfer to a peripheral circuit. Since at least two neighboring memory banks share the latch sense amplifier, the total layout area of the IO sense amplifiers in a memory is reduced, when compared to a memory in which each memory bank has a current sense amplifier and a latch sense amplifier.
REFERENCES:
patent: 5315555 (1994-05-01), Choi
patent: 6046924 (2000-04-01), Isobe et al.
patent: 6104655 (2000-08-01), Tanoi et al.
Heid David W.
Mai Son
Samsung Electronics Co,. Ltd.
Skjerven Morrill & MacPherson LLP
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