Static information storage and retrieval – Read/write circuit – For complementary information
Reexamination Certificate
2000-04-07
2001-11-06
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
For complementary information
C365S208000, C365S230030, C365S194000, C365S196000, C365S204000, C365S051000
Reexamination Certificate
active
06314029
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an input/output sense amplifier which uses signals to vary current gain and to compensate for transmission delay.
2. Description of the Related Art
As integration density of semiconductor memory devices continues to increase, chip size also increases. Due to the increase in chip size, transmission rates of signals may be different depending upon differences in loading due to differences in physical lengths of signal lines. Different transmission rates of signals cause signal skewing, which in turn hinders the overall operating speed of a high-frequency semiconductor memory device.
FIG. 1
is a circuit diagram showing an output portion of a conventional semiconductor memory device. With reference to
FIG. 1
, data of memory cells coupled to a word line selected by a row address are transferred to data input/output lines by activation of a column selection signal selected by a column address. The data transferred to data input/output lines DIOi and DIOiB are output through an input/output sense amplifier (IOSA) to output lines FDOi and FDOiB. The data on the output lines FDOi and FDOiB are output through a driving circuit
10
to a data input/output pad DQ. The data to be output to the data input/output pad DQ is sampled in response to a predetermined sampling signal FRP in the driving circuit
10
.
In a memory device having a plurality of memory blocks, IOSAs are arranged in a position which minimizes the difference between data input and output rates. However, distances from each memory block to the IOSA are typically different. Such a difference in the distance from each memory block to the IOSA causes load differences in signal lines which in turn causes IOSA data skew. To accommodate such data skew, data sampling period in the driving circuit
10
must be reduced. The reduction of the sampling period will be described with reference to the timing diagram of FIG.
2
.
FIG. 2
is a timing diagram showing the reduction of a sampling period due to skew which has occurred between data input to the IOSA from a plurality of memory blocks. Here, an example of an ith memory block and a jth memory block, which is further away from the IOSA than the ith memory block, is described. Referring to
FIG. 2
, because the ith memory block is closer to the IOSA than the jth memory block, data read from the ith memory block is received by the IOSA earlier than data from the jth memory block. Thus, further considering a point in time where the data read from each memory block is sampled and input to a driving circuit
10
, a point in time where data of the ith memory block is loaded onto the output line FDOi and a point in time where data of the jth memory block is loaded onto the output line FDOj are different.
The sampling signal FRP shown in
FIG. 1
, which is generated as a pulse signal, starts data sampling in synchronization with a leading edge of data which has last arrived at the IOSA and terminates the data sampling in synchronization with a trailing edge of data which has first arrived at the IOSA. Thus, as shown in
FIG. 2
, the sampling signal FRP has a sampling period corresponding to an overlapping period between the effective period of the jth memory block data FDOj and the effective period of the ith memory block data FDOi. The overlapping period is shorter than each effective period of the ith and jth memory block data FDOi and FDOj.
Thus, the sampling period of the sampling signal FRP is reduced by the skew between the data input to the IOSA from each memory block, the skew varying according to positions of memory blocks. In addition, such a reduction of the data sampling period may be a serious problem in a memory device which operates at a high frequency.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory device having an input/output sense amplifier capable of minimizing data skew to avoid a reduction in sampling period.
The above and other objects of the present invention may be achieved by a semiconductor memory device comprising: a plurality of sub memory blocks divided by a column address in a memory block; a plurality of data input/output line pairs coupled to the sub memory blocks, for transmitting data in a selected sub memory block; and a plurality of input/output sense amplifiers for sensing and amplifying data from the data input/output line pairs, wherein each of the input/output sense amplifiers has a variable gain characteristic depending on physical distance between the selected sub memory block and the input/output sense amplifiers so as to minimize a difference in delay characteristic according to position of the selected sub memory block.
Preferably, a gain of each of the input/output sense amplifiers is controlled by the column address. Each of the input/output sense amplifiers may comprise: first and second load transistors sources of which are connected to one of the data input/output line pairs, and gates of which are cross-coupled with drains thereof; and at least two amplifiers which are selectively activated in response to the column address, for amplifying data transferred from the first and second load transistors with different gains.
Preferably, each of the at least two amplifiers comprises: first and second transistors each of which has a gate and a drain coupled to each other, drains of the first and second transistors being connected to drains of the first and second load transistors, respectively; and a switching circuit connected between sources of the first and second transistors and a ground voltage, for activating the corresponding amplifier in response to at least one column address having the most significant bit (MSB). Each of the at least two amplifiers may comprise: a first NMOS transistor having a gate and a drain, which are coupled to each other and coupled to a drain of a corresponding one of the first and second load transistors; and a compensation circuit coupled to the first NMOS transistor in parallel, the compensation circuit being controlled by the column address; wherein a switching circuit is coupled between sources of NMOS transistors of the at least two amplifiers and a ground voltage, for activating the input/output sense amplifiers in response to an input/output sense amplifying enable signal.
Each of the input/output sense amplifiers may include load transistor units between input/output lines to which memory cell data is input and output, and the data input/output lines, to provide current to the input/output lines. The load transistor units comprises a first load transistor for supplying current into the input/output lines when a selected sub memory block is relatively close to the input/output sense amplifiers, and a second load transistor for supplying current into the input/output lines when a selected sub memory block is far away from the input/output sense amplifiers.
Preferably, the first load transistor includes: a current driving controller for generating a current driving signal in response to the column address for selecting the sub memory blocks which are relatively close to the input/output sense amplifiers, and a driving signal which is activated in a read mode of the semiconductor memory device; a switching controller for generating a switching signal in response to the column address for selecting the sub memory blocks which are relatively close to the input/output sense amplifiers, and a control signal which is activated in the read mode; a current driver for supplying current to the input/output lines in response to the current driving signal; and a switching portion for connecting the input/output lines and the data input/output lines in response to the switching signal.
Preferably, the second load transistor includes: a current driving controller for generating a current driving signal in response to the column address for selecting the sub memory blocks which are far away from the input/output sense amplifiers, and a drivin
Ko Tae-Young
Rhee Sang-Jae
F. Chau & Associates LLP
Samsung Electronics Co,. Ltd.
Tran Andrew Q.
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