Memory device having high bus efficiency of network,...

Details Memory device having high bus efficiency of network,... Memory device having high bus efficiency of network,...

2005-11-15

2005-11-15

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S189011

Reexamination Certificate

active

06965528

ABSTRACT:
A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.

REFERENCES:
patent: 5548774 (1996-08-01), Maurel
patent: 6317639 (2001-11-01), Hansen
patent: 6898726 (2005-05-01), Lee
patent: 2001/0034805 (2001-10-01), Usui et al.

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