Memory device having common data lines for reading and writing

Details Memory device having common data lines for reading and writing Memory device having common data lines for reading and writing

1990-03-15

1992-02-11

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518904, 3652385, G11C 700, G11C 11409

Patent

active

050880624

ABSTRACT:
A semiconductor memory device includes a memory cell array having plural memory cells disposed in an array. A sense amplifier is provided for selecting a plurality of memory cells from among the plural memory cells of the memory cell array. Data lines are provided coupled to the sense amplifier. Each of the data lines is for transmitting write data to and read data from the memory cell array. A read data latch circuit is provided having a plurality of latch circuits respectively coupled to the data lines. Additionally, a write data latch circuit is provided having a plurality of buffer circuits respectively coupled to the data lines. Thus, a common transmitting path is provided for both inputting data and outputting data from the memory cell array. Upon carrying out a write operation for writing of the write data into the memory cell array, the write data is stored in both the read data latch circuit and the write data latch circuit at the same time.

REFERENCES:
patent: 4633429 (1986-12-01), Lewandowski et al.
patent: 4789960 (1988-12-01), Willis
patent: 4899310 (1990-02-01), Baba et al.
patent: 4935897 (1990-06-01), Kurihara et al.
patent: 4954987 (1990-09-01), Auvinen et al.
patent: 5003475 (1991-03-01), Kerber et al.

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