Memory device having circuitry for initializing and reprogrammin

Details Memory device having circuitry for initializing and reprogrammin Memory device having circuitry for initializing and reprogrammin

1997-01-13

1998-02-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518902, 36523002, G11C 700

Patent

active

057176396

ABSTRACT:
A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates an initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.

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patent: 5436869 (1995-07-01), Yoshida
patent: 5446691 (1995-08-01), North et al.
patent: 5457659 (1995-10-01), Schaefer
patent: 5570320 (1996-10-01), Runas
patent: 5596740 (1997-01-01), Quattromani et al.

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