Memory device having a plurality of sets of data buffers

Details Memory device having a plurality of sets of data buffers Memory device having a plurality of sets of data buffers

1995-03-16

1997-02-11

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518901, 36523008, G11C 700

Patent

active

056027818

ABSTRACT:
When a processor generates an access request to a plurality of continuous addresses to an RAM through a memory control apparatus, in order to enable a high speed process, a register which holds an address for accessing a memory cell and a register which holds an address for accessing a data buffer are separately provided in an RAM having memory cells and a plurality of row correspondence data buffers of the memory cells. A signal line to instruct the presence or absence of the use of the data buffer is provided between the processor and the memory control apparatus. The memory cell and the data buffer are accessed in parallel, thereby realizing a high processing speed. The processor designates so as to preferentially use the data buffer for an RAM access having an address continuity, thereby enabling the data to be accessed at a high speed.

REFERENCES:
patent: 4899310 (1990-02-01), Baba
patent: 5268873 (1993-12-01), Suzuki
patent: 5371711 (1994-12-01), Nakayama
Nikkei Electronics, vol. 6.8, pp. 110-141, 1992, "The Design of CPU board in these days of 100 MHz".
"Proposition of Pseudo Vector Processor by Resister Windows and Super Scalar System," The Japan Symposium of Parallel Processing, JSPP '92 collection of papers, pp. 367-374.
"Examination of Micro Vector Processor Architecture," Information Processing Society of Japan, Research Report 92 ARC 94, pp. 17-24.

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